Maxim DS33R11 11.7 T1/E1/J1 Transceiver Registers, Tr.Mstrreg, Master Mode Register, TEST1 TEST0

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver

11.7 T1/E1/J1 Transceiver Registers

Register Name:		TR.MSTRREG
Register Description:		Master Mode Register
Register Address:		00h
Bit #	7	6	5	4	3	2	1	0
Name	—	—	—	—	TEST1	TEST0	T1/E1	SFTRST
Default	0	0	0	0	0	0	0	0

Bits 2 – 3: Test Mode Bits (TEST0, TEST1) Test modes are used to force the output pins of the transceiver into known states. This can facilitate the checkout of assemblies during the manufacturing process and also be used to isolate devices from shared buses.

TEST1	TEST0	Effect On Output Pins
0	0	Operate normally
0	1	Force all output pins into tri-state (including all I/O pins and parallel port pins)
1	0	Force all output pins low (including all I/O pins except parallel port pins)
1	1	Force all output pins high (including all I/O pins except parallel port pins)

Bit 1: Transceiver Operating Mode (T1/E1) Used to select the operating mode of the framer/formatter (digital) portion of the Transceiver. The operating mode of the LIU must also be programmed.

0 = T1 operation

1 = E1 operation

Bit 0: Software-Issued Reset (SFTRST) A 0-to-1 transition causes the register space in the T1/E1/J1 transceiver to be cleared. A reset clears all configuration and status registers. The bit automatically clears itself when the reset has completed.

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