DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver

Figure 13-17. Transmit-Side Timing

tR

tF

TCLKT

 

tD1

 

TESO

 

TSERI / TSIG /

tSU

 

TDATA

tHD

t D2

TCHCLK

 

TCHBLK

tD2

 

tD2

TSYNC1

tHD

 

tSU

TSYNC2

t D2

TLCLK5

 

 

tHD

TLINK

tSU

 

tCP

tCL

tCH

NOTE 1: TSYNC IS IN THE OUTPUT MODE (IOCR1.1 = 1).

NOTE 2: TSYNC IS IN THE INPUT MODE (IOCR1.1 = 0).

NOTE 3: TSERI IS SAMPLED ON THE FALLING EDGE OF TCLKT WHEN THE TRANSMIT-SIDE ELASTIC STORE IS DISABLED.

NOTE 4: TCHCLK AND TCHBLK ARE SYNCHRONOUS WITH TCLKT WHEN THE TRANSMIT-SIDE ELASTIC STORE IS DISABLED.

333 of 344

Page 333
Image 333
Maxim DS33R11 specifications Transmit-Side Timing