Major Operating Modes | Maxim DS33R11 guide

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver

5 MAJOR OPERATING MODES

Microprocessor control is possible through the 8-bit parallel control port and provides configuration for all the features of the device. The Ethernet Link Transport Engine in the device can be configured for HDLC or X.86 encapsulation.

The integrated transceiver can be software configured for T1, E1, or J1 operation. It is composed of a line interface unit (LIU), framer, two additional HDLC controllers, and a TDM backplane interface, and is controlled via an 8-bit parallel port configured for Intel or Motorola bus operations.

The LIUs are composed of a transmit interface, receive interface, and a jitter attenuator. The transmit interface is responsible for generating the necessary waveshapes for driving the network and providing the correct source impedance depending on the type of media used. T1 waveform generation includes DSX-1 line build-outs as well as CSU line build-outs of -7.5dB, -15dB, and -22.5dB. E1 waveform generation includes G.703 waveshapes for both 75Ω coax and 120Ω twisted cables. The receive interface provides network termination and recovers clock and data from the network. The receive sensitivity adjusts automatically to the incoming signal and can be programmed for 0dB to 43dB or 0dB to 12dB for E1 applications and 0dB to 15dB or 0dB to 36dB for T1 applications. The jitter attenuator removes phase jitter from the transmitted or received signal. The crystal-less jitter attenuator requires only a 2.048MHz MCLK for both E1 and T1 applications (with the option of using a 1.544MHz MCLK in T1 applications) and can be placed in either transmit or receive data paths.

More information on microprocessor control is available in Section 8.1.

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Maxim DS33R11 specifications Major Operating Modes

Contents

Part Temp Range PIN-PACKAGE DS33R11 Table of Contents Integrated T1/E1/J1 Transceiver Device Registers Operating Parameters List of Figures 308 List of Tables Description Page Hdlc Ethernet Mapping X.86 Link Access Protocol for SONET/SDH Ethernet MappingGeneral Microprocessor Interface Sdram Interface Committed Information Rate CIR ControllerMAC Interface Clock Synthesizer T1/E1/J1 Line InterfaceJitter Attenuator TDM Bus 12 T1/E1/J1 Framer Test and Diagnostics T1-Related Telecommunications Specifications Specifications Compliance Ethernet-to-WAN Extension With or Without Framing ESF B8ZSBOC CRC Major Operating Modes JTAG2 Transmit Serial Port Packet HDLC/X.86 CIR Controller Clad Ttip Transmit Framer MUX TringBert Rtip Rring MUX Jtag Host Interface Clock Receive and Transmit T1/E1/J1 LIU Loopback Sync Framer Data Rlclk Sync Rsync Rmsync Rfsync Internal Rdata Signals Rchclk FromSync Signaling Tseri Tsig Rlink Name PIN Type Function Microprocessor Port Pin Functional Description Detailed Pin DescriptionsIOZ Name PIN Type Function Read Data Strobe Intel Mode The DS33R11 drives the data busChip Select for Protocol Conversion Device This pin must be Receive Data 0 through 3 MII Four bits of received data Name PIN Type Function MII/RMII PHY PortReceive Data 0 through 1 Rmii Two bits of received data Reference Clock Output Rmii and MII a derived clock output Reference Clock Rmii and MII When in Rmii mode, all signalsTransmit Data 0 through 3MII TXD 30 is presented Transmit Data 0 through 1RMII Two bits of data TXD Sdram Interface Name PIN Type Function PHY Management BUSSdcs Sdram Data Bus Bits 0 to 31 The 32 pins of the Sdram data T1/E1/J1 Transmit Framer Interface Name PIN Type Function T1/E1/J1 Analog Line Interface T1/E1/J1 Receive Framer Interface Ethernet Mapper Transmit Serial Interface Receive Frame Sync Pre Receive Elastic Store for T1/E1/J1 Receive System Clock for the Transceiver 1.544MHzReceive Multiframe Sync for the T1/E1/J1 Transceiver An T1/E1/J1 FRAMER/LIU Interim Signals Transmit Clock Output from the T1/E1/J1 Framer Buffered Transmit Negative-Data Output Updated on the rising edgeTransmit Positive-Data Output Updated on the rising edge Transmit Elastic Store Output Updated on the rising edge Queue Overflow for Ethernet Mapper This pin goes high when Name PIN Type Function Hardware and Status PinsMode Control for Processor Interface T1/E1/J1 Receive Signaling-Freeze Output Set high when Name PIN Type Function System Clocks Name PIN Type Function Jtag Interface Transmit Analog Signal Ground Connect to the common supply Name PIN Type Function Power SuppliesReceive Analog Positive Supply Connect to 3.3V power supply Receive Analog Signal Ground Connect to the common supply Ball BGA Pinout Functional Description Interrupt and Pin Modes Processor InterfaceRead-Write/Data Strobe Modes Clear on Read Txclk Ethernet Mapper ClocksClocking Options for the Ethernet Interface Rmiimiis Speed DCE/ DTE Refclko Rxclk PIN Output Input Ethernet MAC T1/E1/J1Bert Refclk Arbiter Serial Interface Clock Modes Ethernet Interface Clock Modes Reset Functions Resets and Low Power ModesReset Function Location Comments Example Device Initialization Sequence Initialization and ConfigurationGlobal Resources Per-Port Resources Device Interrupts Pin Drawing Legend Serial Interface Interrupt Information RegistersStatus Registers Information Registers Connections and Queues Arbiter Registers Related to Connections and QueuesRegister Function Flow Control Type ModeOptions for Flow Control Full Duplex Flow Control Host-Managed Flow Control Half Duplex Flow Control Ieee 802.3 Ethernet Frame Ethernet Interface Port Register Name Function Registers Related to Setting the Ethernet Port DTE and DCE Mode Configured as DTE Connected to an Ethernet PHY in MII Mode Ethernet MAC DS33R11 Configured as a DCE in MII Mode MAC Status Registers MAC Control RegistersAddress Register Description Rmii Mode MII Mode Options Bert in the Ethernet Mapper Bert FeaturesPHY MII Management Block and Mdio Interface Receive Pattern Detection Receive Data InterfacePrbs Synchronization Pattern Monitoring Repetitive Pattern SynchronizationPattern Generation Performance Monitoring Update Error InsertionTransmit Packet Processor Receive Packet Processor 11. Hdlc Encapsulation of MAC Frame 12. Laps Encoding of MAC Frames Concept 19 X.86 Encoding and Decoding 13. X.86 Encapsulation of the MAC frame Page Committed Information Rate Controller T1/E1/J1 Clock Map 10.1 T1/E1/J1 Clocks TCSS1 TCSS0 Transmit Clock Source T1/E1/J1 Transmit Clock SourcePer-Channel Operation 10.3 T1/E1/J1 Transceiver Interrupts 10.4.1 T1 Transmit Transparency 10.4 T1 Framer/Formatter Control and StatusAIS-CI and RAI-CI Generation and Detection Alarm SET Criteria Clear Criteria T1 Alarm Criteria10.4.3 T1 Receive-Side Digital-Milliwatt Code Generation ITU Spec 10.5 E1 Framer/Formatter Control and StatusE1 Sync/Resync Criteria Frame or Sync Criteria Resync Criteria Multiframe Level Per-Channel Loopback E1 Alarm CriteriaAutomatic Alarm Generation Alarm SET Criteria Clear Criteria ITU Specification Line-Code Violation Counter TR.LCVCR Error CountersT1 Line Code Violation Counting Options E1 Line-Code Violation Counting Options Counted Framing ModeT1 Path Code Violation Counting Arrangements Path Code Violation Count Register TR.PCVCR Frames Out-of-Sync Count Register TR.FOSCR T1 Frames Out-of-Sync Counting ArrangementsBit Counter TR.EBCR 10.8 DS0 Monitoring Function Processor-Based Receive Signaling Signaling OperationChange-of-State Receive Signaling Freeze Hardware-Based Receive SignalingReceive Signaling Reinsertion at Rsero Force Receive Signaling All Ones 10.9.3.1 T1 Mode Processor-Based Transmit Signaling Channel Phone Hardware-Based Transmit Signaling10.9.3.2 E1 Mode Time Slot Numbering Schemes Maps to Channel Per-Channel Idle Code Generation10. Idle-Code Array Address Mapping Bits 0 to 5 of Iaar Example Idle-Code Programming Examples Elastic Stores Operation 10.12.1.1 T1 Mode10.12.1.2 E1 Mode Channel Blocking Registers Transmit Elastic Store 11. Elastic Store Delay After InitializationMinimum Delay Mode Initialization Register BIT Delay CRC-4 Recalculate Method 10.13 G.706 Intermediate CRC-4 Updating E1 Mode Only Transmit a BOC 10.14 T1 Bit-Oriented Code BOC ControllerTransmit BOC Receive BOC Method 1 Internal Register Scheme Based on Double-Frame Additional Sa and International Si Bit Operation E1 OnlyMethod 2 Internal Register Scheme Based on CRC4 Multiframe Additional Hdlc Controllers in T1/E1/J1 Transceiver Hdlc Configuration 12. Hdlc Controller Registers Hdlc Mapping Fifo ControlRegister Channels Receive Packet-Bytes Available Fifo InformationReceive Hdlc Code Example Overview Legacy FDL Support T1 ModeReceive Section Transmit Section 10.18 D4/SLC-96 Operation Programmable In-Band Loop Code Generation and Detection LIU Operation Line Interface Unit LIUReceiver T1/E1 Receive Level Indicator and Threshold InterruptReceive G.703 Synchronization Signal E1 Mode Monitor Mode Transmit Short-Circuit Detector/Limiter Transmit BPV Error InsertionTransmit G.703 Synchronization Signal E1 Mode Transmitter CMI Code Mark Inversion Option Mclk PrescalerClock Data CMI DS33R11 13. Transformer SpecificationsSpecification Recommended Value Recommended Circuits -7. Basic Interface E1 Transmit Pulse Template 10. Jitter Tolerance E1 Mode T1 Mode Bert Mapping Bert StatusXtald Mclk 15. Simplified Diagram of Bert in Network Direction Bert Alternating Word-Count Rate Bert Error CounterBert Repetitive Pattern Set Bert Bit Counter Number-of-Errors Registers Payload Error-Insertion Function T1 Mode Only14. Transmit Error-Insertion Setup Sequence 15. Error Insertion Examples Fractional T1/E1 Support Programmable Backplane Clock Synthesizer T1 Transmit 114 E1 Transmit 116 E1 Transmit Flow Diagram Port Select Registers Interface Transceiver Register Address MapMapper Chip Global Arbiter Bert Serial Ethernet Interfac Name Register Bit MapsGlobal Ethernet Mapper Register Bit Map Global Ethernet Mapper Register Bit Map Bert Register Bit Map Arbiter Register Bit MapBert Register Bit Map Arbiter Register Bit Map Serial Interface Register Bit Map Serial Interface Register Bit Map 114h Ethernet Interface Register Bit Map Ethernet Interface Register Bit Map MAC Register Bit Map MAC Indirect Register Bit Map 200h 019 T1/E1/J1 Transceiver Register Bit Map Active when CST = 01A 035 050 06A 085 0AD 0AA0AB 0AC 0CD 0CA0CB 0CC 0DF 0DC0DD 0DE GL.IDRL Global Register Definitions for Ethernet MapperGL.IDRH GL.BLR GL.CR1 GL.SRCALS GL.RTCALGL.LIE GL.SIE GL.LISGL.SIS GL.TRQIS GL.TRQIEGL.BIE GL.CON1 GL.BIS GL.BISTEN GL.C1QPR GL.SDMODE1 GL.BISTPF GL.SDMODEWS GL.SDMODE2GL.SDRFTC AR.TQSC1 Arbiter RegistersArbiter Register Bit Descriptions AR.RQSC1 80h Bert RegistersBCR Bert Control Register Bpchr Bpclr BSPB3R BSPB0RBSPB1R BSPB2R BSR Teicr Bsrie Bsrl RBCB0 RBECB0RRBECB1R RBECR2 RBCB2 RBCB1RBCB3 LI.RSTPD Serial Interface RegistersSerial Interface Transmit and Common Registers LI.TSLCR LI.TPPCL LI.LPBK LI.TEPLC LI.TIFGC 0C7h Transmit Errored Packet High Control RegisterCleanup routine LI.TEPHC LI.TPPSRL LI.TPPSRLI.TPPSRIE LI.TPCR1 LI.TPCR0LI.TPCR2 LI.TBCR3 LI.TBCR0LI.TBCR1 LI.TBCR2 LI.THPMUS LI.THPMUU LI.TRX8C 11.5.2 X.86 RegistersLI.TX86EDE LI.TRX86A LI.CIR LI.TRX86SAPIL LI.RSLCR Receive Serial InterfaceLI.RPPCL LI.RMPSCH LI.RMPSCLLI.RPPSR Repl Rapl Ripdl Rspdl Rlpdl Repcl Rapcl Rspcl LI.RPPSRLReceive Packet Processor Status Register Latched 105h Repie Rapie Ripdie Rspdie Rlpdie Repcie Rapcie Rspcie Receive Packet Processor Status Register Interrupt EnableLI.RPPSRIE 106h LI.RPCB1 LI.RPCB0LI.RPCB2 LI.RFPCB1 LI.RFPCB0LI.RFPCB2 LI.RAPCB1 LI.RAPCB0LI.RAPCB2 LI.RSPCB1 LI.RSPCB0LI.RSPCB2 LI.RBC3 LI.RBC0LI.RBC1 LI.RBC2 LI.RAC3 LI.RAC0LI.RAC1 LI.RAC2 LI.RHPMUS LI.RHPMUULI.RX86S LI.TQLT LI.RX86LSIELI.TQHT 127h LI.TQTIE126h LI.TQCTLS SU.MACRADH Ethernet Interface RegistersEthernet Interface Register Bit Descriptions SU.MACRADL SU.MACWD0 SU.MACRD1SU.MACRD2 SU.MACRD3 SU.MACAWL SU.MACWD1SU.MACWD2 SU.MACWD3 SU.MACRWC SU.MACAWH SU.GCR SU.LPBK Ncfq Tprhbc Tprcb SU.TFRCTransmit Frame Resend Control 151h SU.TFSH SU.TFSL SU.RFSB1 SU.RFSB0SU.RFSB2 157h SU.RFSB3MCF SU.RQHT SU.RMFSRLSU.RMFSRH SU.RQLT SU.QCRLS SU.QRIE Ucfr Cfrr Lerr Crcerr DBR Miier BFR SU.RFRCReceive Frame Rejection Control 15Eh SU.MACCR MAC Registers Bit Random Number Generator Bits Used SU.MACMIIA SU.MACMIID SU.MACFCR SU.MMCCTRL 010Dh ReservedMAC Reserved Control Register 010Ch indirect 0113h 0110h indirect0111h 0112h 0201h SU.RxFrmCtrMAC All Frames Received Counter 0200h indirect 0205h SU.RxFrmOkCtrMAC Frames Received OK Counter 0204h indirect 0301h SU.TxFrmCtrMAC All Frames Transmitted Counter 0300h indirect 0309h SU.TxBytesCtrMAC All Bytes Transmitted Counter 0308h indirect 030Dh SU.TxBytesOkCtrMAC Bytes Transmitted OK Counter 030Ch indirect 0335h SU.TxFrmUndrMAC Transmit Frame Under Run Counter 0334h indirect 0339h SU.TxBdFrmCtrMAC All Frames Aborted Counter 0338h indirect TR.MSTRREG Master Mode RegisterEffect On Output Pins 11.7 T1/E1/J1 Transceiver Registers Bit 1 Tsync I/O Select Tsio 0 = Tsync is an input Configuration RegisterBit 6 Rsync Mode Select 2 RSMS2 TR.IOCR1 TR.IOCR2 OOF2 OOF1 TR.T1RCR1 TR.T1RCR2 Bit 6 Receive Frame Mode Select RFM 0 = D4 framing modeBit 5 Receive B8ZS Enable RB8ZS Bit 1 Receive Japanese CRC6 Enable RJC TR.T1TCR1 TR.T1TCR2 Bit 7 Transmit B8ZS Enable TB8ZSTB8ZS TSLC96 Tzse FBCT2 FBCT1 TD4YM TB7ZS T1 Common Control Register Bit 2 Transmit Frame Mode Select TFM 0 = D4 framing modeTR.SSIE1 T1 Mode TR.T1CCR1 Software Signaling Insertion Enable TR.SSIE1 E1 ModeTR.SSIE2 E1 Mode Lcaw TR.SSIE3 E1 ModeTR.SSIE4 TR.T1RDMR2 TR.T1RDMR1TR.T1RDMR3 TR.INFO1 TR.IDR RL3 RL2 RL1 RL0 TR.INFO211h Bits 0 3 Receive Level Bits RL0 to RL3. Real-time bits TR.IIR1 TR.INFO3TR.IIR2 16h Ilut Timer Rscos Jalt Lrcl Tcle Tocd LolitcTR.SR1 Status Register Bit 7 Input Level Under Threshold Ilut 0 = interrupt masked TR.IMR1Interrupt Mask Register 17h 18h TR.SR2Ryelc RUA1C Frclc Rlosc 19h TR.IMR2Bit 0 Receive Loss-of-Sync Condition Rlos 1Ah TR.SR3Lspare LDN LUP Lotc Lorc V52LNK Rdma RRA TR.IMR3 Bit 2 Receive Multiframe Event RMF TR.SR41Ch RAIS-CI Rsao Rsaz TMF TAF RMF Rcmf RAF Bit 3 Transmit Align Frame Event TAF 0 = interrupt masked TR.IMR41Dh Bit 7 Receive AIS-CI Event RAIS-CI 1Eh TR.SR5Tesf Tesem Tslip Resf Resem Rslip 1Fh TR.IMR5 20h, 22h TR.SR6, TR.SR7Hdlc #1 Status Register Hdlc #2 Status Register TR.IMR6, TR.IMR7 PS2 PS1 PS0 TR.INFO5, TR.INFO6TR.INFO4 TR.IMR8 TR.SR8 26h TR.SR9Bbed Bbco BEC0 BRA1 BRA0 Brlos Bsync TR.IMR9 Rsaoics Rsrcs Rfcs Brcs Thscs Peics Tfcs Btcs TR.PCPRPer-Channel Pointer Register 28h TR.PCDR4 TR.PCDR1TR.PCDR2 TR.PCDR3 Hdlc #2 Receive Control 31h, 32h TR.INFO7TR.H1RC, TR.H2RC Hdlc #1 Receive Control TR.E1RCR2 TR.E1RCR1 TR.E1TCR1 TR.BOCC TR.E1TCR2RBF1 RBF0 MSB LSB TR.RSINFO1, TR.RSINFO2, TR.RSINFO3, TR.RSINFO4TR.RSCSE1, TR.RSCSE2, TR.RSCSE3, TR.RSCSE4 TR.SIGCR Signaling Control RegisterGrsre RFE RFF Rccs Tccs Frsao Bit 2 Pcvcr Fs-Bit Error-Report Enable Fsbe Error-Counter Configuration RegisterBit 5 Error-Counter Update Select Ecus Bit 4 Error-Accumulation Mode Select Eams TR.PCVCR2 TR.LCVCR1TR.LCVCR2 TR.PCVCR1 TR.EBCR2 TR.FOSCR1TR.FOSCR2 TR.EBCR1 Liuc LLB RLB PLB FLB TR.LBCRLoopback Control Register 4Ah TR.PCLR4 TR.PCLR1TR.PCLR2 TR.PCLR3 Tesalgn Tesr Tesmdm Tese Resalgn Resr Resmdm Rese TR.ESCRElastic Store Control Register 4Fh TR.TS1 to TR.TS16 Transmit Signaling Registers E1 Mode, CAS Format50h to 5Fh Transmit Signaling Registers E1 Mode, CCS Format TR.TS1 to TR.TS12 Transmit Signaling Registers T1 Mode, ESF Format50h to 5Bh CH4-A CH4-B Transmit Signaling Registers T1 Mode, D4 FormatCH2-A CH2-B CH1-A CH1-B 60h to 6Bh Receive Signaling Registers T1 Mode, ESF FormatReceive Signaling Registers T1 Mode, D4 Format TR.RS1 to TR.RS12 60h to 6Fh Receive Signaling Registers E1 Mode, CAS FormatReceive Signaling Registers E1 Mode, CCS Format TR.RS1 to TR.RS16 TCSS1 TCSS0 TR.CCR1 BPCS1 BPCS0 TR.CCR2TR.CCR3 RLT3 RLT2 RLT1 RLT0 TR.CCR4TR.TDS0SEL TR.RDS0SEL TR.TDS0MTR.RDS0M TR.LIC1 T1, Impedance Match Off Bit 6 Automatic Gain Control Enable AgceNetwork Mode GC5 GC4 GC3 GC2 GC1 GC0 TR.TLBC Bit 7 E1/T1 Select ETS TR.LIC279h ETS Lirst Ibpv TUA1 Jamux Scld Clds MM1 MM0 TR.LIC3 TT1 TT0 TR.LIC4MPS1 MPS0 Jamux Mclk MPS1 MPS0 Jamux TR.TCICE1 TR.IAARGric Gtic Function TR.PCICR TR.RCICE1 TR.TCICE2TR.TCICE3 TR.TCICE4 TR.RCBR1 TR.RCICE2TR.RCICE3 TR.RCICE4 TR.RCBR3 TR.RCBR2TR.RCBR4 TR.TCBR4 TR.TCBR1TR.TCBR2 TR.TCBR3 90h, A0h TR.H1TC, TR.H2TCHdlc #1 Transmit Control Hdlc #2 Transmit Control TFLWM2 TFLWM1 TFLWM0 TR.H1FC, TR.H2FCRFHWM2 RFHWM1 RFHWM0 Bit 2 Receive Hdlc Channel Select Bit Register Name TR.H1RCS1, TR.H1RCS2, TR.H1RCS3, TR.H1RCS4A2h, A3h, A4h, A5h Bit 3 Receive Hdlc Channel Select Bit RCB8SE RCB7SE RCB6SE RCB5SE RCB4SE RCB3SE RCB2SE RCB1SE TR.H1RTSBS, TR.H2RTSBSHdlc # 1 Receive Time Slot Bits/Sa Bits Select Hdlc # 2 Receive Time Slot Bits/Sa Bits Select 96h, A6h Bit 2 Transmit Hdlc Channel Select Bit Register Name TR.H1TCS1, TR.H1TCS2, TR.H1TCS3, TR.H1TCS4A7h, A8h, A9h, AAh Bit 3 Transmit Hdlc Channel Select Bit TR.H1RPBA, TR.H2RPBA TR.H1TTSBS, TR.H2TTSBS TR.H1RF, TR.H2RF TR.H1TF, TR.H2TF RUP2 RUP1 RUP0 TR.H1TFBA, TR.H2TFBATR.IBCC TC1 TC0 B8h TR.TCD1TR.TCD2 Transmit Code Definition Register Receive Up-Code Definition Register TR.RUPCD2BAh TR.RDNCD2 TR.RDNCD1Receive Down-Code Definition Register BBh RSC2 RSC1 RSC0 TR.RSCCIn-Band Receive Spare Control Register BDh TR.RSCD2 TR.RSCD1 RBOC5 RBOC4 RBOC3 RBOC2 RBOC1 RBOC0 TR.RFDL TR.BOCC.4 =Receive FDL Register C0h TR.RFDLM1, TR.RFDLM2 TR.TFDL TR.RNAF TR.RAFReceive Align Frame Register C6h TR.RSiNAF TR.RSiAFReceived Si Bits of the Align Frame C8h TR.RRA TR.RSa6 TR.RSa5Received Sa5 Bits CCh TR.RSa8 TR.RSa7Received Sa7 Bits CEh TR.TNAF TR.TAF TR.TSiNAF TR.TSiAFTransmit Si Bits of the Align Frame D2h TR.TRA TR.TSa6 TR.TSa5Transmitted Sa5 Bits D6h TR.TSa8 TR.TSa7Transmit Sa7 Bits D8h TR.BAWC TR.TSACR TR.BRP4 TR.BRP1TR.BRP2 TR.BRP3 PS1 PS0 TR.BC1 EIB2 EIB1 EIB0 TR.BC2RPL3 RPL2 RPL1 RPL0 TR.BBC4 TR.BBC1TR.BBC2 TR.BBC3 EC9 EC8 TR.BEC1EC7 EC6 EC5 EC4 EC3 EC2 EC1 EC0 TR.BEC2 TR.BIC ER3 ER2 ER1 ER0 TR.ERC TR.NOE2 Number-of-ErrorsTR.NOE1 ECh TR.NOEL2 TR.NOEL1 Tx Serial Interface Functional Timing Functional Serial I/O Timing MII and Rmii Interfaces Transmit Byte Sync Functional Timing MII Transmit Half Duplex with a Collision Functional Timing FRAME# RSYNC1 Rfsync RSYNC2 Rsync FRAME# Rfsync RSYNC1 Rsync 2 RSYNC3 Rchclk RCHBLK1 Rsync RfsyncRchclk Rchblk Rchclk RCHBLK4 Rsysclk Rser O Tchclk Tchblk FRAME# TSYNC1 Tssync Tsync TSYNC3 Tchclk Tchblk 2,3 FRAME# Rfsync Rsync 12.4 E1 Mode Rchclk RCHBLK3 Rsysclk RseroRSYNC2 Rmsync RSYNC3 Rchclk Rchblk Rmsync Rsync FRAME# TSYNC1 Tssync Rsync Tsync Rchclk Tchclk Rchblk TchblkTSYNC2 Tssync Tchclk Tchblk 26. Transmit-Side Boundary Timing Elastic Store Disabled 312 Parameter Symbol Conditions MIN TYP MAX Units DC Electrical CharacteristicsRecommended DC Operating Conditions AIR Flow THETA-JA Thermal Characteristics -3. Thermal CharacteristicsTheta-JA vs. Airflow Parameter MIN TYP MAX MIN TYP MAX Parameter SymbolMII Interface Transmit MII Interface 10Mbps 100Mbps Receive MII Interface Timing Receive MII Interface Transmit Rmii Interface Timing Rmii Interface Transmit Rmii Interface Receive Rmii Interface Timing Receive Rmii Interface Mdio Interface Parameter Symbol MIN TYP MAX UnitsMDC Mdio Tclke Tsero Tden Tbsync Transmit WAN Interface 10. Transmit WAN Interface Rclki Rseri Rden Rbsync Receive WAN Interface 11. Receive WAN Interface 100 MHz Sdram Timing 12. Sdram Interface Timing SDA, SBA SdataRAS, Scas SWE, Sdcs Parameter Symbol MIN TYP MAX Units Intel Bus Read Timing Modec = 11. Motorola Bus Read Timing Modec = RMSYNC, Rsync RCHBLK, Rfsync Rfsync / Rmsync Rsero / Rdata / Rsig See Note Rsero / RsigRchblk Rmsync Rsync 15. Receive Line Interface Timing Delay Rclko to Bpclk 16. Receive Timing Delay Rclko to Bpclk TSERI, TSIG, TDATA, TPOSI, Tnegi Parameter Symbol Conditions MIN TYP E1 MAX Units 17. Transmit-Side Timing 18. Transmit-Side Timing, Elastic Store Enabled Jtag Interface Timing 17. Jtag Interface Timing 20. Jtag Interface Timing Diagram Jtag Information Jtag TAP Controller State Machine Description Capture-IR Update-DRUpdate-IR Select-IR-Scan Instruction Register TAP Controller State Diagram Instruction Selected Register Instruction Codes Instruction Codes for Ieee 1149.1 Architecture Bypass Register Jtag ID Codes ID Code StructureTest Registers Boundary Scan Register Bypass Idcode State Jtag Functional Timing 15.1 256-Ball BGA 27mm x 27mm 56-G6004-001 Package Information Revision Description Document Revision History