DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver

Figure 12-19.Transmit-Side 2.048MHz Boundary Timing (Elastic Store Enabled)

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Figure 12-20.Receive-Side Timing

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Figure 12-21.Receive-Side Boundary Timing (with Elastic Store Disabled)

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Figure 12-22.Receive-Side Boundary Timing, RSYSCLK = 1.544MHz (E-Store Enabled)

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Figure 12-23.Receive-Side Boundary Timing, RSYSCLK = 2.048MHz (E-Store Enabled)

309

Figure 12-24. G.802 Timing, E1 Mode Only

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Figure 12-25.Transmit-Side Timing

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Figure 12-26.Transmit-Side Boundary Timing (Elastic Store Disabled)

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Figure 12-27.Transmit-Side Boundary Timing, TSYSCLK = 1.544MHz (Elastic Store Enabled)

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Figure 12-28.Transmit-Side Boundary Timing, TSYSCLK = 2.048MHz (Elastic Store Enabled)

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Figure 13-1. Transmit MII Interface Timing

315

Figure 13-2. Receive MII Interface Timing

316

Figure 13-3. Transmit RMII Interface Timing

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Figure 13-4. Receive RMII Interface Timing

318

Figure 13-5. MDIO Interface Timing

319

Figure 13-6. Transmit WAN Interface Timing

320

Figure 13-7. Receive WAN Interface Timing

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Figure 13-8. SDRAM Interface Timing

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Figure 13-9. Intel Bus Read Timing (MODEC = 00)

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Figure 13-10. Intel Bus Write Timing (MODEC = 00)

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Figure 13-11. Motorola Bus Read Timing (MODEC = 01)

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Figure 13-12. Motorola Bus Write Timing (MODEC = 01)

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Figure 13-13.Receive-Side Timing

328

Figure 13-14.Receive-Side Timing, Elastic Store Enabled

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Figure 13-15. Receive Line Interface Timing

330

Figure 13-16. Receive Timing Delay RCLKO to BPCLK

331

Figure 13-17.Transmit-Side Timing

333

Figure 13-18.Transmit-Side Timing, Elastic Store Enabled

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Figure 13-19. Transmit Line Interface Timing

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Figure 13-20. JTAG Interface Timing Diagram

335

Figure 14-1. JTAG Functional Block Diagram

336

Figure 14-2. TAP Controller State Diagram

339

Figure 14-3. JTAG Functional Timing

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