Manuals / Maxim / Computer Equipment / Switch

Maxim DS33R11 specifications Arbiter Register Bit Map, Bert Register Bit Map

Models: DS33R11

1 344

Download 344 pages 19.08 Kb

Page 119

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver

11.1.2 Arbiter Register Bit Map

Table 11-3. Arbiter Register Bit Map

ADDR	NAME	BIT 7	BIT 6	BIT 5	BIT 4	BIT 3	BIT 2	BIT 1	BIT 0
40h	AR.RQSC1	RQSC7	RQSC6	RQSC5	RQSC4	RQSC3	RQSC2	RQSC1	RQSC0
41h	AR.TQSC1	TQSC7	TQSC6	TQSC5	TQSC4	TQSC3	TQSC2	TQSC1	TQSC0

11.1.3 BERT Register Bit Map

Table 11-4. BERT Register Bit Map

ADDR	NAME	BIT 7	BIT 6	BIT 5	BIT 4
080h	BCR	-	PMU	RNPL	RPIC
081h	Reserved	-	-	-	-
082h	BPCLR	-	QRSS	PTS	PLF4
083h	BPCHR	-	-	-	PTF4
084h	BSPB0R	BSP7	BSP6	BSP5	BSP4
085h	BSPB1R	BSP15	BSP14	BSP13	BSP12
086h	BSPB2R	BSP23	BSP22	BSP21	BSP20
087h	BSPB3R	BSP31	BSP30	BSP29	BSP28
088h	TEICR	-	-	TIER2	TIER1
08Ah	Reserved	-	-	-	-
08Bh	Reserved	-	-	-	-
08Ch	BSR	-	-	-	-
08Dh	Reserved	-	-	-	-
08Eh	BSRL	-	-	-	-
08Fh	Reserved	-	-	-	-
90h	BSRIE	-	-	-	-
91h	Reserved	-	-	-	-
92h	Reserved	-	-	-	-
93h	Reserved	-	-	-	-
94h	RBECB0R	BEC7	BEC6	BEC5	BEC4
95h	RBECB1R	BEC15	BEC14	BEC13	BEC12
96h	RBECB2R	BEC23	BEC22	BEC21	BEC20
97h	Reserved	-	-	-	-
98h	RBCB0	BC7	BC6	BC5	BC4
99h	RBCB1	BC15	BC14	BC13	BC12
9Ah	RBCB2	BC23	BC22	BC21	BC20
9Bh	RBCB3	BC31	BC30	BC29	BC28
9Ch	Reserved	-	-	-	-
9Dh	Reserved	-	-	-	-
9Eh	Reserved	-	-	-	-
9Fh	Reserved	-	-	-	-

BIT 3 MPR

-

PLF3

PTF3

BSP3

BSP11

BSP19

BSP27

TIER0

-

-

PMS

-

PMSL

-

PMSIE

-

-

-

BEC3

BEC11

BEC19

-

BC3

BC11

BC19

BC27

-

-

-

-

BIT 2	BIT 1	BIT 0
APRD	TNPL	TPIC
-	-	-
PLF2	PLF1	PLF0
PTF2	PTF1	PTF0
BSP2	BSP1	BSP0
BSP10	BSP9	BSP8
BSP18	BSP17	BSP16
BSP26	BSP25	BSP24
BEI	TSEI	-
-	-	-
-	-	-
-	BEC	OOS
-	-	-
BEL	BECL	OOSL
-	-	-
BEIE	BECIE	OOSIE
-	-	-
-	-	-
-	-	-
BEC2	BEC1	BEC0
BEC10	BEC9	BEC8
BEC18	BEC17	BEC16
-	-	-
BC2	BC1	BC0
BC10	BC9	BC8
BC18	BC17	BC16
BC26	BC25	BC24
-	-	-
-	-	-
-	-	-
-	-	-

119 of 344

Image 119

Maxim DS33R11 specifications Arbiter Register Bit Map, Bert Register Bit Map

Contents

Part Temp Range PIN-PACKAGE DS33R11Table of Contents Integrated T1/E1/J1 Transceiver Device Registers Operating Parameters List of Figures 308 List of Tables Description Page Hdlc Ethernet Mapping X.86 Link Access Protocol for SONET/SDH Ethernet MappingGeneral Microprocessor InterfaceMAC Interface Committed Information Rate CIR ControllerSdram Interface Jitter Attenuator T1/E1/J1 Line InterfaceClock Synthesizer TDM Bus 12 T1/E1/J1 FramerTest and Diagnostics T1-Related Telecommunications Specifications Specifications ComplianceEthernet-to-WAN Extension With or Without Framing ESF B8ZSBOC CRCMajor Operating Modes JTAG2 Transmit Serial Port Packet HDLC/X.86 CIR Controller Clad Ttip Transmit Framer MUX TringBert Rtip Rring MUXJtag Host Interface ClockReceive and Transmit T1/E1/J1 LIU Loopback Sync Framer DataRlclk Sync Rsync Rmsync Rfsync Internal Rdata Signals Rchclk FromSync Signaling Tseri Tsig RlinkIOZ Pin Functional Description Detailed Pin DescriptionsName PIN Type Function Microprocessor Port Chip Select for Protocol Conversion Device This pin must be Read Data Strobe Intel Mode The DS33R11 drives the data busName PIN Type Function Receive Data 0 through 1 Rmii Two bits of received data Name PIN Type Function MII/RMII PHY PortReceive Data 0 through 3 MII Four bits of received data Reference Clock Output Rmii and MII a derived clock output Reference Clock Rmii and MII When in Rmii mode, all signalsTransmit Data 0 through 3MII TXD 30 is presented Transmit Data 0 through 1RMII Two bits of data TXDSdcs Name PIN Type Function PHY Management BUSSdram Interface Sdram Data Bus Bits 0 to 31 The 32 pins of the Sdram data T1/E1/J1 Transmit Framer Interface Name PIN Type Function T1/E1/J1 Analog Line InterfaceT1/E1/J1 Receive Framer Interface Ethernet Mapper Transmit Serial InterfaceReceive Multiframe Sync for the T1/E1/J1 Transceiver An Receive System Clock for the Transceiver 1.544MHzReceive Frame Sync Pre Receive Elastic Store for T1/E1/J1 T1/E1/J1 FRAMER/LIU Interim Signals Transmit Clock Output from the T1/E1/J1 Framer Buffered Transmit Negative-Data Output Updated on the rising edgeTransmit Positive-Data Output Updated on the rising edge Transmit Elastic Store Output Updated on the rising edgeQueue Overflow for Ethernet Mapper This pin goes high when Name PIN Type Function Hardware and Status PinsMode Control for Processor Interface T1/E1/J1 Receive Signaling-Freeze Output Set high whenName PIN Type Function System Clocks Name PIN Type Function Jtag Interface Transmit Analog Signal Ground Connect to the common supply Name PIN Type Function Power SuppliesReceive Analog Positive Supply Connect to 3.3V power supply Receive Analog Signal Ground Connect to the common supplyBall BGA Pinout Functional Description Interrupt and Pin Modes Processor InterfaceRead-Write/Data Strobe Modes Clear on ReadTxclk Ethernet Mapper ClocksClocking Options for the Ethernet Interface Rmiimiis Speed DCE/ DTE Refclko Rxclk PIN Output InputBert Refclk Arbiter T1/E1/J1Ethernet MAC Serial Interface Clock Modes Ethernet Interface Clock ModesReset Function Location Comments Resets and Low Power ModesReset Functions Example Device Initialization Sequence Initialization and ConfigurationGlobal Resources Per-Port ResourcesDevice Interrupts Pin Drawing LegendSerial Interface Interrupt Information RegistersStatus Registers Information RegistersConnections and Queues Register Function Registers Related to Connections and QueuesArbiter Options for Flow Control Type ModeFlow Control Full Duplex Flow Control Host-Managed Flow Control Half Duplex Flow ControlIeee 802.3 Ethernet Frame Ethernet Interface PortRegister Name Function Registers Related to Setting the Ethernet PortDTE and DCE Mode Configured as DTE Connected to an Ethernet PHY in MII ModeEthernet MAC DS33R11 Configured as a DCE in MII ModeAddress Register Description MAC Control RegistersMAC Status Registers Rmii Mode MII Mode OptionsPHY MII Management Block and Mdio Interface Bert FeaturesBert in the Ethernet Mapper Prbs Synchronization Receive Data InterfaceReceive Pattern Detection Pattern Generation Repetitive Pattern SynchronizationPattern Monitoring Transmit Packet Processor Error InsertionPerformance Monitoring Update Receive Packet Processor 11. Hdlc Encapsulation of MAC Frame 12. Laps Encoding of MAC Frames Concept 19 X.86 Encoding and Decoding13. X.86 Encapsulation of the MAC frame Page Committed Information Rate Controller T1/E1/J1 Clock Map 10.1 T1/E1/J1 ClocksTCSS1 TCSS0 Transmit Clock Source T1/E1/J1 Transmit Clock SourcePer-Channel Operation 10.3 T1/E1/J1 Transceiver InterruptsAIS-CI and RAI-CI Generation and Detection 10.4 T1 Framer/Formatter Control and Status10.4.1 T1 Transmit Transparency 10.4.3 T1 Receive-Side Digital-Milliwatt Code Generation T1 Alarm CriteriaAlarm SET Criteria Clear Criteria ITU Spec 10.5 E1 Framer/Formatter Control and StatusE1 Sync/Resync Criteria Frame or Sync Criteria Resync Criteria Multiframe LevelPer-Channel Loopback E1 Alarm CriteriaAutomatic Alarm Generation Alarm SET Criteria Clear Criteria ITU SpecificationLine-Code Violation Counter TR.LCVCR Error CountersT1 Line Code Violation Counting Options E1 Line-Code Violation Counting OptionsCounted Framing ModeT1 Path Code Violation Counting Arrangements Path Code Violation Count Register TR.PCVCRBit Counter TR.EBCR T1 Frames Out-of-Sync Counting ArrangementsFrames Out-of-Sync Count Register TR.FOSCR 10.8 DS0 Monitoring Function Change-of-State Signaling OperationProcessor-Based Receive Signaling Receive Signaling Freeze Hardware-Based Receive SignalingReceive Signaling Reinsertion at Rsero Force Receive Signaling All Ones10.9.3.1 T1 Mode Processor-Based Transmit SignalingChannel Phone Hardware-Based Transmit Signaling10.9.3.2 E1 Mode Time Slot Numbering SchemesMaps to Channel Per-Channel Idle Code Generation10. Idle-Code Array Address Mapping Bits 0 to 5 of IaarExample Idle-Code Programming ExamplesElastic Stores Operation 10.12.1.1 T1 Mode10.12.1.2 E1 Mode Channel Blocking RegistersTransmit Elastic Store 11. Elastic Store Delay After InitializationMinimum Delay Mode Initialization Register BIT DelayCRC-4 Recalculate Method 10.13 G.706 Intermediate CRC-4 Updating E1 Mode OnlyTransmit a BOC 10.14 T1 Bit-Oriented Code BOC ControllerTransmit BOC Receive BOCMethod 2 Internal Register Scheme Based on CRC4 Multiframe Additional Sa and International Si Bit Operation E1 OnlyMethod 1 Internal Register Scheme Based on Double-Frame Additional Hdlc Controllers in T1/E1/J1 Transceiver Hdlc Configuration12. Hdlc Controller Registers Register Channels Fifo ControlHdlc Mapping Receive Hdlc Code Example Fifo InformationReceive Packet-Bytes Available Receive Section Legacy FDL Support T1 ModeOverview Transmit Section 10.18 D4/SLC-96 OperationProgrammable In-Band Loop Code Generation and Detection Receiver Line Interface Unit LIULIU Operation T1/E1 Receive Level Indicator and Threshold InterruptReceive G.703 Synchronization Signal E1 Mode Monitor ModeTransmit Short-Circuit Detector/Limiter Transmit BPV Error InsertionTransmit G.703 Synchronization Signal E1 Mode TransmitterClock Data CMI Mclk PrescalerCMI Code Mark Inversion Option DS33R11 13. Transformer SpecificationsSpecification Recommended Value Recommended Circuits -7. Basic InterfaceE1 Transmit Pulse Template 10. Jitter Tolerance E1 Mode T1 ModeXtald Mclk Bert StatusBert Mapping 15. Simplified Diagram of Bert in Network Direction Bert Alternating Word-Count Rate Bert Error CounterBert Repetitive Pattern Set Bert Bit CounterNumber-of-Errors Registers Payload Error-Insertion Function T1 Mode Only14. Transmit Error-Insertion Setup Sequence 15. Error Insertion ExamplesFractional T1/E1 Support Programmable Backplane Clock SynthesizerT1 Transmit 114 E1 Transmit 116 E1 Transmit Flow DiagramPort Select Registers Interface Transceiver Register Address MapMapper Chip Global Arbiter Bert Serial Ethernet InterfacName Register Bit MapsGlobal Ethernet Mapper Register Bit Map Global Ethernet Mapper Register Bit MapBert Register Bit Map Arbiter Register Bit MapBert Register Bit Map Arbiter Register Bit MapSerial Interface Register Bit Map Serial Interface Register Bit Map114h Ethernet Interface Register Bit Map Ethernet Interface Register Bit MapMAC Register Bit Map MAC Indirect Register Bit Map200h 019 T1/E1/J1 Transceiver Register Bit Map Active when CST =01A 035 050 06A 085 0AD 0AA0AB 0AC0CD 0CA0CB 0CC0DF 0DC0DD 0DEGL.IDRH Global Register Definitions for Ethernet MapperGL.IDRL GL.BLR GL.CR1GL.LIE GL.RTCALGL.SRCALS GL.SIS GL.LISGL.SIE GL.BIE GL.TRQIEGL.TRQIS GL.CON1 GL.BISGL.BISTEN GL.C1QPRGL.SDMODE1 GL.BISTPFGL.SDRFTC GL.SDMODE2GL.SDMODEWS AR.TQSC1 Arbiter RegistersArbiter Register Bit Descriptions AR.RQSC180h Bert RegistersBCR Bert Control RegisterBpchr BpclrBSPB3R BSPB0RBSPB1R BSPB2RBSR TeicrBsrie BsrlRBCB0 RBECB0RRBECB1R RBECR2RBCB3 RBCB1RBCB2 LI.RSTPD Serial Interface RegistersSerial Interface Transmit and Common Registers LI.TSLCRLI.TPPCL LI.LPBKLI.TEPLC LI.TIFGC0C7h Transmit Errored Packet High Control RegisterCleanup routine LI.TEPHCLI.TPPSRIE LI.TPPSRLI.TPPSRL LI.TPCR2 LI.TPCR0LI.TPCR1 LI.TBCR3 LI.TBCR0LI.TBCR1 LI.TBCR2LI.THPMUS LI.THPMUULI.TRX8C 11.5.2 X.86 RegistersLI.TX86EDE LI.TRX86ALI.CIR LI.TRX86SAPILLI.RPPCL Receive Serial InterfaceLI.RSLCR LI.RPPSR LI.RMPSCLLI.RMPSCH Repl Rapl Ripdl Rspdl Rlpdl Repcl Rapcl Rspcl LI.RPPSRLReceive Packet Processor Status Register Latched 105hRepie Rapie Ripdie Rspdie Rlpdie Repcie Rapcie Rspcie Receive Packet Processor Status Register Interrupt EnableLI.RPPSRIE 106hLI.RPCB2 LI.RPCB0LI.RPCB1 LI.RFPCB2 LI.RFPCB0LI.RFPCB1 LI.RAPCB2 LI.RAPCB0LI.RAPCB1 LI.RSPCB2 LI.RSPCB0LI.RSPCB1 LI.RBC3 LI.RBC0LI.RBC1 LI.RBC2LI.RAC3 LI.RAC0LI.RAC1 LI.RAC2LI.RX86S LI.RHPMUULI.RHPMUS LI.TQHT LI.RX86LSIELI.TQLT 127h LI.TQTIE126h LI.TQCTLSSU.MACRADH Ethernet Interface RegistersEthernet Interface Register Bit Descriptions SU.MACRADLSU.MACWD0 SU.MACRD1SU.MACRD2 SU.MACRD3SU.MACAWL SU.MACWD1SU.MACWD2 SU.MACWD3SU.MACRWC SU.MACAWHSU.GCR SU.LPBKNcfq Tprhbc Tprcb SU.TFRCTransmit Frame Resend Control 151hSU.TFSH SU.TFSLSU.RFSB2 SU.RFSB0SU.RFSB1 MCF SU.RFSB3157h SU.RQHT SU.RMFSRLSU.RMFSRH SU.RQLTSU.QCRLS SU.QRIEUcfr Cfrr Lerr Crcerr DBR Miier BFR SU.RFRCReceive Frame Rejection Control 15EhSU.MACCR MAC RegistersBit Random Number Generator Bits Used SU.MACMIIA SU.MACMIID SU.MACFCR SU.MMCCTRL 010Dh ReservedMAC Reserved Control Register 010Ch indirect0113h 0110h indirect0111h 0112h0201h SU.RxFrmCtrMAC All Frames Received Counter 0200h indirect0205h SU.RxFrmOkCtrMAC Frames Received OK Counter 0204h indirect0301h SU.TxFrmCtrMAC All Frames Transmitted Counter 0300h indirect0309h SU.TxBytesCtrMAC All Bytes Transmitted Counter 0308h indirect030Dh SU.TxBytesOkCtrMAC Bytes Transmitted OK Counter 030Ch indirect0335h SU.TxFrmUndrMAC Transmit Frame Under Run Counter 0334h indirect0339h SU.TxBdFrmCtrMAC All Frames Aborted Counter 0338h indirectTR.MSTRREG Master Mode RegisterEffect On Output Pins 11.7 T1/E1/J1 Transceiver RegistersBit 1 Tsync I/O Select Tsio 0 = Tsync is an input Configuration RegisterBit 6 Rsync Mode Select 2 RSMS2 TR.IOCR1TR.IOCR2 OOF2 OOF1 TR.T1RCR1TR.T1RCR2 Bit 6 Receive Frame Mode Select RFM 0 = D4 framing modeBit 5 Receive B8ZS Enable RB8ZS Bit 1 Receive Japanese CRC6 Enable RJCTR.T1TCR1 TB8ZS TSLC96 Tzse FBCT2 FBCT1 TD4YM TB7ZS Bit 7 Transmit B8ZS Enable TB8ZSTR.T1TCR2 T1 Common Control Register Bit 2 Transmit Frame Mode Select TFM 0 = D4 framing modeTR.SSIE1 T1 Mode TR.T1CCR1TR.SSIE2 E1 Mode TR.SSIE1 E1 ModeSoftware Signaling Insertion Enable TR.SSIE4 TR.SSIE3 E1 ModeLcaw TR.T1RDMR3 TR.T1RDMR1TR.T1RDMR2 TR.INFO1 TR.IDRRL3 RL2 RL1 RL0 TR.INFO211h Bits 0 3 Receive Level Bits RL0 to RL3. Real-time bitsTR.IIR2 TR.INFO3TR.IIR1 16h Ilut Timer Rscos Jalt Lrcl Tcle Tocd LolitcTR.SR1 Status RegisterBit 7 Input Level Under Threshold Ilut 0 = interrupt masked TR.IMR1Interrupt Mask Register 17hRyelc RUA1C Frclc Rlosc TR.SR218h Bit 0 Receive Loss-of-Sync Condition Rlos TR.IMR219h Lspare LDN LUP Lotc Lorc V52LNK Rdma RRA TR.SR31Ah TR.IMR3 Bit 2 Receive Multiframe Event RMF TR.SR41Ch RAIS-CI Rsao Rsaz TMF TAF RMF Rcmf RAFBit 3 Transmit Align Frame Event TAF 0 = interrupt masked TR.IMR41Dh Bit 7 Receive AIS-CI Event RAIS-CITesf Tesem Tslip Resf Resem Rslip TR.SR51Eh 1Fh TR.IMR520h, 22h TR.SR6, TR.SR7Hdlc #1 Status Register Hdlc #2 Status RegisterTR.IMR6, TR.IMR7 TR.INFO4 TR.INFO5, TR.INFO6PS2 PS1 PS0 TR.IMR8 TR.SR8Bbed Bbco BEC0 BRA1 BRA0 Brlos Bsync TR.SR926h TR.IMR9 Rsaoics Rsrcs Rfcs Brcs Thscs Peics Tfcs Btcs TR.PCPRPer-Channel Pointer Register 28hTR.PCDR4 TR.PCDR1TR.PCDR2 TR.PCDR3Hdlc #2 Receive Control 31h, 32h TR.INFO7TR.H1RC, TR.H2RC Hdlc #1 Receive ControlTR.E1RCR2 TR.E1RCR1TR.E1TCR1 RBF1 RBF0 TR.E1TCR2TR.BOCC TR.RSCSE1, TR.RSCSE2, TR.RSCSE3, TR.RSCSE4 TR.RSINFO1, TR.RSINFO2, TR.RSINFO3, TR.RSINFO4MSB LSB Grsre RFE RFF Rccs Tccs Frsao Signaling Control RegisterTR.SIGCR Bit 2 Pcvcr Fs-Bit Error-Report Enable Fsbe Error-Counter Configuration RegisterBit 5 Error-Counter Update Select Ecus Bit 4 Error-Accumulation Mode Select EamsTR.PCVCR2 TR.LCVCR1TR.LCVCR2 TR.PCVCR1TR.EBCR2 TR.FOSCR1TR.FOSCR2 TR.EBCR1Liuc LLB RLB PLB FLB TR.LBCRLoopback Control Register 4AhTR.PCLR4 TR.PCLR1TR.PCLR2 TR.PCLR3Tesalgn Tesr Tesmdm Tese Resalgn Resr Resmdm Rese TR.ESCRElastic Store Control Register 4Fh50h to 5Fh Transmit Signaling Registers E1 Mode, CAS FormatTR.TS1 to TR.TS16 Transmit Signaling Registers E1 Mode, CCS Format 50h to 5Bh Transmit Signaling Registers T1 Mode, ESF FormatTR.TS1 to TR.TS12 CH4-A CH4-B Transmit Signaling Registers T1 Mode, D4 FormatCH2-A CH2-B CH1-A CH1-B60h to 6Bh Receive Signaling Registers T1 Mode, ESF FormatReceive Signaling Registers T1 Mode, D4 Format TR.RS1 to TR.RS1260h to 6Fh Receive Signaling Registers E1 Mode, CAS FormatReceive Signaling Registers E1 Mode, CCS Format TR.RS1 to TR.RS16TCSS1 TCSS0 TR.CCR1TR.CCR3 TR.CCR2BPCS1 BPCS0 TR.TDS0SEL TR.CCR4RLT3 RLT2 RLT1 RLT0 TR.RDS0M TR.TDS0MTR.RDS0SEL TR.LIC1 T1, Impedance Match Off Bit 6 Automatic Gain Control Enable AgceNetwork Mode GC5 GC4 GC3 GC2 GC1 GC0 TR.TLBCBit 7 E1/T1 Select ETS TR.LIC279h ETS Lirst Ibpv TUA1 Jamux Scld CldsMM1 MM0 TR.LIC3TT1 TT0 TR.LIC4MPS1 MPS0 Jamux Mclk MPS1 MPS0 JamuxTR.TCICE1 TR.IAARGric Gtic Function TR.PCICRTR.RCICE1 TR.TCICE2TR.TCICE3 TR.TCICE4TR.RCBR1 TR.RCICE2TR.RCICE3 TR.RCICE4TR.RCBR4 TR.RCBR2TR.RCBR3 TR.TCBR4 TR.TCBR1TR.TCBR2 TR.TCBR390h, A0h TR.H1TC, TR.H2TCHdlc #1 Transmit Control Hdlc #2 Transmit ControlRFHWM2 RFHWM1 RFHWM0 TR.H1FC, TR.H2FCTFLWM2 TFLWM1 TFLWM0 Bit 2 Receive Hdlc Channel Select Bit Register Name TR.H1RCS1, TR.H1RCS2, TR.H1RCS3, TR.H1RCS4A2h, A3h, A4h, A5h Bit 3 Receive Hdlc Channel Select BitRCB8SE RCB7SE RCB6SE RCB5SE RCB4SE RCB3SE RCB2SE RCB1SE TR.H1RTSBS, TR.H2RTSBSHdlc # 1 Receive Time Slot Bits/Sa Bits Select Hdlc # 2 Receive Time Slot Bits/Sa Bits Select 96h, A6hBit 2 Transmit Hdlc Channel Select Bit Register Name TR.H1TCS1, TR.H1TCS2, TR.H1TCS3, TR.H1TCS4A7h, A8h, A9h, AAh Bit 3 Transmit Hdlc Channel Select BitTR.H1RPBA, TR.H2RPBA TR.H1TTSBS, TR.H2TTSBSTR.H1RF, TR.H2RF TR.H1TF, TR.H2TFRUP2 RUP1 RUP0 TR.H1TFBA, TR.H2TFBATR.IBCC TC1 TC0B8h TR.TCD1TR.TCD2 Transmit Code Definition RegisterBAh TR.RUPCD2Receive Up-Code Definition Register TR.RDNCD2 TR.RDNCD1Receive Down-Code Definition Register BBhRSC2 RSC1 RSC0 TR.RSCCIn-Band Receive Spare Control Register BDhTR.RSCD2 TR.RSCD1RBOC5 RBOC4 RBOC3 RBOC2 RBOC1 RBOC0 TR.RFDL TR.BOCC.4 =Receive FDL Register C0hTR.RFDLM1, TR.RFDLM2 TR.TFDLTR.RNAF TR.RAFReceive Align Frame Register C6hTR.RSiNAF TR.RSiAFReceived Si Bits of the Align Frame C8hTR.RRA TR.RSa6 TR.RSa5Received Sa5 Bits CChTR.RSa8 TR.RSa7Received Sa7 Bits CEhTR.TNAF TR.TAFTR.TSiNAF TR.TSiAFTransmit Si Bits of the Align Frame D2hTR.TRA TR.TSa6 TR.TSa5Transmitted Sa5 Bits D6hTR.TSa8 TR.TSa7Transmit Sa7 Bits D8hTR.BAWC TR.TSACRTR.BRP4 TR.BRP1TR.BRP2 TR.BRP3PS1 PS0 TR.BC1RPL3 RPL2 RPL1 RPL0 TR.BC2EIB2 EIB1 EIB0 TR.BBC4 TR.BBC1TR.BBC2 TR.BBC3EC9 EC8 TR.BEC1EC7 EC6 EC5 EC4 EC3 EC2 EC1 EC0 TR.BEC2TR.BIC ER3 ER2 ER1 ER0 TR.ERCTR.NOE2 Number-of-ErrorsTR.NOE1 EChTR.NOEL2 TR.NOEL1Tx Serial Interface Functional Timing Functional Serial I/O TimingMII and Rmii Interfaces Transmit Byte Sync Functional TimingMII Transmit Half Duplex with a Collision Functional Timing FRAME# RSYNC1 Rfsync RSYNC2 Rsync FRAME# Rfsync RSYNC1 Rsync 2 RSYNC3Rchclk Rchblk Rsync RfsyncRchclk RCHBLK1 Rchclk RCHBLK4 Rsysclk Rser OTchclk Tchblk FRAME# TSYNC1 Tssync Tsync TSYNC3Tchclk Tchblk 2,3 FRAME# Rfsync Rsync 12.4 E1 ModeRchclk RCHBLK3 Rsysclk RseroRSYNC2 Rmsync RSYNC3 Rchclk Rchblk Rmsync RsyncTSYNC2 Rsync Tsync Rchclk Tchclk Rchblk TchblkFRAME# TSYNC1 Tssync Tssync Tchclk Tchblk 26. Transmit-Side Boundary Timing Elastic Store Disabled312 Recommended DC Operating Conditions DC Electrical CharacteristicsParameter Symbol Conditions MIN TYP MAX Units AIR Flow THETA-JA Thermal Characteristics -3. Thermal CharacteristicsTheta-JA vs. Airflow Parameter MIN TYP MAXMIN TYP MAX Parameter SymbolMII Interface Transmit MII Interface 10Mbps 100MbpsReceive MII Interface Timing Receive MII InterfaceTransmit Rmii Interface Timing Rmii Interface Transmit Rmii InterfaceReceive Rmii Interface Timing Receive Rmii InterfaceMDC Mdio Parameter Symbol MIN TYP MAX UnitsMdio Interface Tclke Tsero Tden Tbsync Transmit WAN Interface 10. Transmit WAN InterfaceRclki Rseri Rden Rbsync Receive WAN Interface 11. Receive WAN Interface100 MHz Sdram Timing 12. Sdram Interface TimingSDA, SBA SdataRAS, Scas SWE, SdcsParameter Symbol MIN TYP MAX Units Intel Bus Read Timing Modec = 11. Motorola Bus Read Timing Modec = RMSYNC, Rsync RCHBLK, RfsyncRfsync / Rmsync Rsero / Rdata / RsigRchblk Rmsync Rsync Rsero / RsigSee Note 15. Receive Line Interface Timing Delay Rclko to Bpclk 16. Receive Timing Delay Rclko to BpclkTSERI, TSIG, TDATA, TPOSI, Tnegi Parameter Symbol Conditions MIN TYP E1 MAX Units17. Transmit-Side Timing 18. Transmit-Side Timing, Elastic Store Enabled Jtag Interface Timing 17. Jtag Interface Timing 20. Jtag Interface Timing DiagramJtag Information Jtag TAP Controller State Machine Description Capture-IR Update-DRUpdate-IR Select-IR-ScanInstruction Register TAP Controller State DiagramInstruction Selected Register Instruction Codes Instruction Codes for Ieee 1149.1 ArchitectureBypass Register Jtag ID Codes ID Code StructureTest Registers Boundary Scan RegisterBypass Idcode State Jtag Functional Timing15.1 256-Ball BGA 27mm x 27mm 56-G6004-001 Package InformationRevision Description Document Revision History