DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver

Figure 6-2. Block Diagram of T1/E1/J1 Transceiver

 

 

CLOCK

 

 

 

 

 

 

 

 

 

 

 

CLOCK

 

EXTERNAL ACCESS

 

 

 

 

 

 

 

 

TO RECEIVE SIGNALS

 

 

 

 

 

 

 

ADAPTER

 

 

 

 

 

 

 

 

 

 

 

 

 

 

REMOTE LOOPBACK

 

HDB3 / B8ZS

PAYLOAD LOOPBACK

BACKPLANE

 

 

 

RX

 

JITTER ATTENUATOR

MUX

 

SYNC

CLOCK SYNTH

 

 

 

LIU

 

 

SINGALING

 

 

 

 

 

 

 

 

BACKPLANE

 

NETWORK

 

LOCAL LOOPBACK

 

ALARM DET

 

 

 

 

 

HDLCs

BACKPLANE

 

 

 

 

 

 

 

 

 

FRAMER

INTERFACE

 

 

 

 

CIRCUIT

 

TX

 

SINGALING

 

T1/E1/J1

LIU

MUX

LOOPBACKFRAMER

HDLCs

 

 

 

CRC GEN

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

HDB3 / B8ZS

 

 

 

 

 

LIU

 

EXTERNAL ACCESS

 

FRAMER

 

BACKPLANE

 

 

 

 

TO TRANSMIT SIGNALS

 

 

 

 

 

 

 

 

 

 

INTERFACE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

JTAG

HOST INTERFACE

ESIB

 

 

 

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Maxim DS33R11 specifications Clock, Jtag Host Interface