Maxim DS33R11 Parameter Symbol Conditions MIN TYP E1 MAX Units, TSERI, TSIG, TDATA, TPOSI, Tnegi

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver

13.11 AC Characteristics: Transmit Side

Table 13-16. AC Characteristics: Transmit Side

(VDD = 3.3V ±5%, TA = 0°C to +85°C.) (Note 1, Figure 13-17, Figure 13-18, and Figure 13-19)

PARAMETER	SYMBOL	CONDITIONS	MIN	TYP (E1) MAX	UNITS
TCLKT Period	tCP			488 (E1)	ns
				648 (T1)
TCLKT Pulse Width	tCH		20	0.5 tCP	ns
	tCL		20	0.5 tCP
TDCLKI Period	tLP			488 (E1)	ns
				648 (T1)
TDCLKI Pulse Width	tLH		20	0.5 tLP	ns
	tLL		20	0.5 tLP
TSYSCLK Period	tSP	(Note 2)		648	ns
		(Note 3)		448
TSYSCLK Pulse Width	tSP		20	0.5 tSP	ns
			20	0.5 tSP
TSYNC or TSSYNC Setup to TCLKT or	tSU		20		ns
TSYSCLK Falling
TSYNC or TSSYNC Pulse Width	tPW		50		ns
TSERI, TSIG, TDATA, TPOSI, TNEGI	tSU		20		ns
Setup to TCLKT, TSYSCLK, TDCLKI
Falling
TSERI, TSIG, TDATA Hold from TCLKT	tHD		20		ns
or TSYSCLK Falling
TPOSI, TNEGI Hold from TDCLKI	tHD		20		ns
Falling
TCLKT, TDCLKI or TSYSCLK Rise and	tR, tF			25	ns
Fall Times
Delay TCLKO to TPOSO, TNEGO Valid	tDD			50	ns
Delay TCLKT to TESO, UT-UTDO Valid	tD1			50	ns
Delay TCLKT to TCHBLK, TCHCLK,	tD2			50	ns
TSYNC
Delay TSYSCLK to TCHCLK, TCHBLK	tD3			22	ns

Note 1: Timing parameters in this table are guaranteed by design (GBD).

Note 2: TSYSCLK = 1.544MHz.

Note 3: TSYSCLK = 2.048MHz.

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