DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
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(VDD = 3.3V ±5%, TA = 0°C to +85°C.) (Note 1, Figure 13-17, Figure 13-18, and Figure 13-19)
PARAMETER SYMBOL CONDITIONS MIN TYP (E1) MAX UNITS
488 (E1)
TCLKT Period tCP 648 (T1)
ns
tCH 20 0.5 tCP
TCLKT Pulse Width tCL 20 0.5 tCP ns
488 (E1)
TDCLKI Period tLP 648 (T1) ns
tLH 20 0.5 tLP
TDCLKI Pulse Width tLL 20 0.5 tLP ns
(Note 2) 648
TSYSCLK Period tSP (Note 3) 448 ns
20 0.5 tSP
TSYSCLK Pulse Width tSP 20 0.5 tSP ns
TSYNC or TSSYNC Setup to TCLKT or
TSYSCLK Falling tSU
20 ns
TSYNC or TSSYNC Pulse Width tPW 50 ns
TSERI, TSIG, TDATA, TPOSI, TNEGI
Setup to TCLKT, TSYSCLK, TDCLKI
Falling
tSU
20 ns
TSERI, TSIG, TDATA Hold from TCLKT
or TSYSCLK Falling tHD
20 ns
TPOSI, TNEGI Hold from TDCLKI
Falling tHD
20 ns
TCLKT, TDCLKI or TSYSCLK Rise and
Fall Times tR, tF
25 ns
Delay TCLKO to TPOSO, TNEGO Valid tDD 50 ns
Delay TCLKT to TESO, UT-UTDO Valid tD1 50 ns
Delay TCLKT to TCHBLK, TCHCLK,
TSYNC tD2
50 ns
Delay TSYSCLK to TCHCLK, TCHBLK tD3 22 ns
Note 1: Timing parameters in this table are guaranteed by design (GBD).
Note 2: TSYSCLK = 1.544MHz.
Note 3: TSYSCLK = 2.048MHz.