Maxim DS33R11 specifications TR.INFO2, 11h, Bits 0 3 Receive Level Bits RL0 to RL3. Real-time bits

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver

Register Name:		TR.INFO2
Register Description:		Information Register 2
Register Address:		11h
Bit #	7	6	5	4	3	2	1	0
Name	BSYNC	BD	TCLE	TOCD	RL3	RL2	RL1	RL0
Default	0	0	0	0	0	0	0	0

Bit 7: BERT Real-Time Synchronization Status (BSYNC). Real-time status of the synchronizer (this bit is not latched). This bit is set when the incoming pattern matches for 32 consecutive bit positions. It is cleared when six or more bits out of 64 are received in error. Refer to BSYNC in the BERT status register, TR.SR9, for an interrupt- generating version of this signal.

Bit 6: BOC Detected (BD). A real-time bit that is set high when the BOC detector is presently seeing a valid sequence and set low when no BOC is currently being detected.

Bit 5: Transmit Current-Limit Exceeded (TCLE). A real-time bit that is set when the 50mA (RMS) current limiter is activated, whether the current limiter is enabled or not.

Bit 4: Transmit Open-Circuit Detect (TOCD). A real-time bit that is set when the device detects that the TTIP and TRING outputs are open-circuited.

Bits 0 – 3: Receive Level Bits (RL0 to RL3). Real-time bits

RL3	RL2	RL1	RL0	Receive Level (dB)
0	0	0	0	Greater than -2.5
0	0	0	1	-2.5 to -5.0
0	0	1	0	-5.0 to -7.5
0	0	1	1	-7.5 to -10.0
0	1	0	0	-10.0 to -12.5
0	1	0	1	-12.5 to -15.0
0	1	1	0	-15.0 to -17.5
0	1	1	1	-17.5 to -20.0
1	0	0	0	-20.0 to -22.5
1	0	0	1	-22.5 to -25.0
1	0	1	0	-25.0 to -27.5
1	0	1	1	-27.5 to -30.0
1	1	0	0	-30.0 to -32.5
1	1	0	1	-32.5 to -35.0
1	1	1	0	-35.0 to -37.5
1	1	1	1	Less than -37.5

NOTE: RL0 through RL3 only indicate the signal range as specified by the EGL bit in TR.LIC1. Example; if EGL = 1 and in T1 mode, RL0 through RL3 will only indicate a signal range of >-2.5dB to –15dB even if the signal is < - 15dB.

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