DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver

 

 

 

TABLE OF CONTENTS

 

1

DESCRIPTION

9

2

FEATURE HIGHLIGHTS

11

 

2.1

GENERAL

11

 

2.2

MICROPROCESSOR INTERFACE

11

 

2.3

HDLC ETHERNET MAPPING

11

 

2.4

X.86 (LINK ACCESS PROTOCOL FOR SONET/SDH) ETHERNET MAPPING

11

 

2.5

ADDITIONAL HDLC CONTROLLERS IN THE INTEGRATED T1/E1/J1 TRANSCEIVER

12

 

2.6

COMMITTED INFORMATION RATE (CIR) CONTROLLER

12

 

2.7

SDRAM INTERFACE

12

 

2.8

MAC INTERFACE

12

 

2.9

T1/E1/J1 LINE INTERFACE

13

 

2.10

CLOCK SYNTHESIZER

13

 

2.11

JITTER ATTENUATOR

13

 

2.12

T1/E1/J1 FRAMER

14

 

2.13

TDM BUS

14

 

2.14

TEST AND DIAGNOSTICS

15

 

2.15

SPECIFICATIONS COMPLIANCE

16

3

APPLICATIONS

17

4

ACRONYMS AND GLOSSARY

18

5

MAJOR OPERATING MODES

19

6

BLOCK DIAGRAMS

20

7

PIN DESCRIPTIONS

25

 

7.1

PIN FUNCTIONAL DESCRIPTION

25

8

FUNCTIONAL DESCRIPTION

41

 

8.1

PROCESSOR INTERFACE

42

 

8.1.1

Read-Write/Data Strobe Modes

42

 

8.1.2

Clear on Read

42

 

8.1.3 Interrupt and Pin Modes

42

9

ETHERNET MAPPER

43

 

9.1

ETHERNET MAPPER CLOCKS

43

 

9.1.1 Ethernet Interface Clock Modes

45

 

9.1.2 Serial Interface Clock Modes

45

 

9.2

RESETS AND LOW POWER MODES

46

 

9.3

INITIALIZATION AND CONFIGURATION

47

 

9.4

GLOBAL RESOURCES

47

 

9.5

PER-PORTRESOURCES

47

 

9.6

DEVICE INTERRUPTS

48

 

9.7

INTERRUPT INFORMATION REGISTERS

50

 

9.8

STATUS REGISTERS

50

 

9.9

INFORMATION REGISTERS

50

 

9.10

SERIAL INTERFACE

50

 

9.11

CONNECTIONS AND QUEUES

51

 

9.12

ARBITER

52

 

9.13

FLOW CONTROL

53

 

9.13.1 Full Duplex Flow Control

54

 

9.13.2 Half Duplex Flow Control

55

 

9.13.3

Host-Managed Flow Control

55

 

9.14

ETHERNET INTERFACE PORT

56

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Maxim DS33R11 specifications Table of Contents