Maxim DS33R11 specifications Line Interface Unit LIU, LIU Operation, Receiver

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver

10.20 Line Interface Unit (LIU)

The LIU contains three sections: the receiver that handles clock and data recovery, the transmitter that waveshapes and drives the T1 line, and the jitter attenuator. These three sections are controlled by the line interface control registers (LIC1–LIC4), which are described in the following sections. The LIU has its own T1/E1 mode-select bit and can operate independently of the framer function.

The transceiver can switch between T1 or E1 networks without changing external components on the transmit or receive side. Figure 10-7 shows a network connection using minimal components. In this configuration, the transceiver can connect to T1, J1, or E1 (75Ω or 120Ω) without component changes. The receiver can adjust the 120Ω termination to 100Ω or 75Ω. The transmitter can adjust its output impedance to provide high return-loss characteristics for 120Ω, 100Ω, and 75Ω lines. Other components can be added to this configuration to meet safety and network protection requirements (Section 10.24).

10.20.1 LIU Operation

The analog AMI/HDB3 waveform off the E1 line or the AMI/B8ZS waveform off of the T1 line is transformer- coupled into the RTIP and RRING pins of the device. The user has the option to use internal termination, software selectable for 75Ω/100Ω/120Ω applications, or external termination. The LIU recovers clock and data from the analog signal and passes it through the jitter-attenuation mux outputting the received line clock at RDCLKO and bipolar or NRZ data at RPOSO and RNEGO. The transceiver contains an active filter that reconstructs the analog- received signal for the nonlinear losses that occur in transmission. The receive circuitry also is configurable for various monitor applications. The device has a usable receive sensitivity of 0dB to -43dB for E1 and 0dB to -36dB for T1, which allow the device to operate on 0.63mm (22AWG) cables up to 2.5km (E1) and 6k feet (T1) in length. Data input at TPOSI and TNEGI is sent through the jitter-attenuation mux to the waveshaping circuitry and line driver. The transceiver drives the E1 or T1 line from the TTIP and TRING pins through a coupling transformer. The line driver can handle both CEPT 30/ISDN-PRI lines for E1 and long-haul (CSU) or short-haul (DSX-1) lines for T1.

10.20.2 Receiver

The receiver contains a digital clock recovery system. The device couples to the receive E1 or T1 twisted pair (or coaxial cable in 75Ω E1 applications) through a 1:1 transformer. See Table 10-13 for transformer details. The device has the option of using software-selectable termination requiring only a single fixed pair of termination resistors.

The transceiver’s LIU is designed to be fully software selectable for E1 and T1, requiring no change to any external resistors for the receive side. The receive side allows the user to configure the transceiver for 75Ω, 100Ω, or 120Ω receive termination by setting the RT1 (TR.LIC4.1) and RT0 (TR.LIC4.0) bits. When using the internal termination feature, the resistors labeled R in Figure 10-7 should be 60Ω each. If external termination is used, RT1 and RT0 should be set to 0 and the resistors labeled R in Figure 10-7 should be 37.5Ω, 50Ω, or 60Ω each, depending on the line impedance.

There are two ranges of user-selectable receive sensitivity for T1 and E1. The EGL bit of TR.LIC1 (TR.LIC1.4) selects the full or limited sensitivity. The resultant E1 or T1 clock derived from MCLK is multiplied by 16 through an internal PLL and fed to the clock recovery system. The clock recovery system uses the clock from the PLL circuit to form a 16-times over-sampler that is used to recover the clock and data. This over-sampling technique offers outstanding performance to meet jitter tolerance specifications shown in Figure 10-10.

Normally, the clock that is output at the RCLKO pin is the recovered clock from the E1 AMI/HDB3 or T1 AMI/B8ZS waveform presented at the RTIP and RRING inputs. If the jitter attenuator is placed in the receive path (as is the case in most applications), the jitter attenuator restores the RCLKO to an approximate 50% duty cycle. If the jitter attenuator is either placed in the transmit path or is disabled, the RCLKO output can exhibit slightly shorter high cycles of the clock. This is because of the highly over-sampled digital-clock recovery circuitry. See the Receive AC Timing Characteristics in Section 13.9 for more details. When no signal is present at RTIP and RRING, a receive carrier loss (RCL) condition occurs and the RCLKO is derived from the JACLK source.

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