DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver

9.14.1

DTE and DCE Mode

58

9.15

ETHERNET MAC

59

9.15.1

MII Mode Options

61

9.15.2

RMII Mode

61

9.15.3

PHY MII Management Block and MDIO Interface

62

9.16

BERT IN THE ETHERNET MAPPER

62

9.16.1

Receive Data Interface

63

9.16.2

Repetitive Pattern Synchronization

64

9.16.3

Pattern Monitoring

64

9.16.4

Pattern Generation

64

9.17

TRANSMIT PACKET PROCESSOR

65

9.18

RECEIVE PACKET PROCESSOR

66

9.19

X.86 ENCODING AND DECODING

68

9.20

COMMITTED INFORMATION RATE CONTROLLER

71

10 INTEGRATED T1/E1/J1 TRANSCEIVER

72

10.1

T1/E1/J1 CLOCKS

72

10.2

PER-CHANNELOPERATION

73

10.3

T1/E1/J1 TRANSCEIVER INTERRUPTS

73

10.4

T1 FRAMER/FORMATTER CONTROL AND STATUS

74

10.4.1

T1 Transmit Transparency

74

10.4.2

AIS-CI and RAI-CI Generation and Detection

74

10.4.3

T1 Receive-SideDigital-Milliwatt Code Generation

75

10.5

E1 FRAMER/FORMATTER CONTROL AND STATUS

76

10.5.1

Automatic Alarm Generation

77

10.6

PER-CHANNELLOOPBACK

77

10.7

ERROR COUNTERS

78

10.7.1

Line-Code Violation Counter (TR.LCVCR)

78

10.7.2

Path Code Violation Count Register (TR.PCVCR)

79

10.7.3

Frames Out-of-Sync Count Register (TR.FOSCR)

80

10.7.4

E-Bit Counter (TR.EBCR)

80

10.8

DS0 MONITORING FUNCTION

81

10.9

SIGNALING OPERATION

82

10.9.1

Processor-Based Receive Signaling

82

10.9.2

Hardware-Based Receive Signaling

83

10.9.3

Processor-Based Transmit Signaling

84

10.9.4

Hardware-Based Transmit Signaling

85

10.10PER-CHANNELIDLE CODE GENERATION

86

10.10.1 Idle-Code Programming Examples

87

10.11CHANNEL BLOCKING REGISTERS

88

10.12ELASTIC STORES OPERATION

88

10.12.1 Receive Elastic Store

88

10.12.2 Transmit Elastic Store

89

10.12.3 Elastic Stores Initialization

89

10.12.4 Minimum Delay Mode

89

10.13G.706 INTERMEDIATE CRC-4 UPDATING (E1 MODE ONLY)

90

10.14T1 BIT-ORIENTEDCODE (BOC) CONTROLLER

91

10.14.1 Transmit BOC

91

10.15RECEIVE BOC

91

10.16ADDITIONAL (SA) AND INTERNATIONAL (SI) BIT OPERATION (E1 ONLY)

92

10.16.1 Method 1: Internal Register Scheme Based on Double-Frame

92

10.16.2 Method 2: Internal Register Scheme Based on CRC4 Multiframe

92

10.17ADDITIONAL HDLC CONTROLLERS IN T1/E1/J1 TRANSCEIVER

93

10.17.1 HDLC Configuration

93

10.17.2 FIFO Control

95

10.17.3 HDLC Mapping

95

 

 

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Maxim DS33R11 specifications Integrated T1/E1/J1 Transceiver