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Maxim DS33R11 Figure 13-15. Receive Line Interface Timing

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DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver

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Figure 13-15. Receive Line Interface Timing

RPOSI, RNEGI

RDCLKI

tCP

tSU

tHD

tDD

RPOSO, RNEGO

RDCLKO

tLP

Contents

Main DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceive r www.maxim-ic.com DS33R11 GENERAL DESCRIPTION TABLE OF CONTENTS Page Page Page LIST OF FIGURES Page LIST OF TABLES 1 DESCRIPTION Page 2 FEATURE HIGHLIGHTS 2.1 General 2.2 Microprocessor Interface 2.3 HDLC Ethernet Mapping 2.4 X.86 (Link Access Protocol for SONET/SDH) Ethernet Mapping 2.5 Additional HDLC Controllers in the Integrated T1/E1/J1 Transceiver 2.6 Committed Information Rate (CIR) Controller 2.7 SDRAM Interface 2.8 MAC Interface 2.9 T1/E1/J1 Line Interface 2.10 Clock Synthesizer 2.11 Jitter Attenuator 2.12 T1/E1/J1 Framer Japanese J1 support o o 2.13 TDM Bus 2.14 Test and Diagnostics 2.15 Specifications Compliance Table 2-1. T1-Related Telecommunications Specifications 3 APPLICATIONS Figure 3-1. Ethernet-to-WAN Extension (With or Without Framing) 4 ACRONYMS AND GLOSSARY 5 MAJOR OPERATING MODES 6 BLOCK DIAGRAMS Figure 6-1. Main Block Diagram MAPPER ETHERNET T1/E1/J1 TRANSCEIVER LIU FRAMER BACKPLANE INTERFACE Figure 6-3. Receive and Transmit T1/E1/J1 LIU Figure 6-4. Receive and Transmit T1/E1/J1 Framer Figure 6-5. T1/E1/J1 Backplane Interface 7 PIN DESCRIPTIONS 7.1 Pin Functional Description Table 7-1. Detailed Pin Descriptions Page Page Page Page Page Page Page Page Page Page Page Page Page Page Figure 7-1. 256-Ball BGA Pinout 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 A U M F 8 FUNCTIONAL DESCRIPTION 8.1 Processor Interface 8.1.1 Read-Write/Data Strobe Modes 8.1.2 Clear on Read 8.1.3 Interrupt and Pin Modes 9 ETHERNET MAPPER 9.1 Ethernet Mapper Clocks Table 9-1. Clocking Options for the Ethernet Interface Figure 9-1. Clocking for the DS33R11 MAPPER ETHERNET T1/E1/J1 TRANSCEIVER 9.1.1 Ethernet Interface Clock Modes 9.1.2 Serial Interface Clock Modes 9.2 Resets and Low Power Modes Table 9-2. Reset Functions 9.3 Initialization and Configuration 9.4 Global Resources 9.5 Per-Port Resources 9.6 Device Interrupts DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 49 of 344 Figure 9-2. Device Interrupt Information Flow Diagram GL.LIS GL.TRQIS LI.TQCTLS 9.7 Interrupt Information Registers 9.8 Status Registers 9.9 Information Registers 9.10 Serial Interface 9.11 Connections and Queues Table 9-3. Registers Related to Connections and Queues 9.12 Arbiter 9.13 Flow Control Table 9-4. Options for Flow Control 9.13.1 Full Duplex Flow Control Figure 9-3. Flow Control Using Pause Control Frame 9.13.2 Half Duplex Flow Control 9.13.3 Host-Managed Flow Control 9.14 Ethernet Interface Port Figure 9-4. IEEE 802.3 Ethernet Frame Table 9-5. Registers Related to Setting the Ethernet Port 9.14.1 DTE and DCE Mode Figure 9-5. Configured as DTE Connected to an Ethernet PHY in MII Mode Figure 9-6. DS33R11 Configured as a DCE in MII Mode 9.15 Ethernet MAC Table 9-6. MAC Control Registers Table 9-7. MAC Status Registers 9.15.1 MII Mode Options 9.15.2 RMII Mode Figure 9-7. RMII Interface 9.15.3 PHY MII Management Block and MDIO Interface Figure 9-8. MII Management Frame 9.16 BERT in the Ethernet Mapper BERT Features 9.16.1 Receive Data Interface Figure 9-9. PRBS Synchronization State Diagram Sync LoadVerify 9.16.2 Repetitive Pattern Synchronization Figure 9-10. Repetitive Pattern Synchronization State Diagram Sync MatchVerify 9.16.3 Pattern Monitoring 9.16.4 Pattern Generation 9.17 Transmit Packet Processor 9.18 Receive Packet Processor Figure 9-11. HDLC Encapsulation of MAC Frame 9.19 X.86 Encoding and Decoding Figure 9-12. LAPS Encoding of MAC Frames Concept Figure 9-13. X.86 Encapsulation of the MAC frame Page 9.20 Committed Information Rate Controller 10 INTEGRATED T1/E1/J1 TRANSCEIVER 10.1 T1/E1/J1 Clocks Figure 10-1. T1/E1/J1 Clock Map Table 10-1. T1/E1/J1 Transmit Clock Source 10.2 Per-Channel Operation 10.3 T1/E1/J1 Transceiver Interrupts 10.4 T1 Framer/Formatter Control and Status 10.4.1 T1 Transmit Transparency 10.4.2 AIS-CI and RAI-CI Generation and Detection 10.4.3 T1 Receive-Side Digital-Milliwatt Code Generation Table 10-2. T1 Alarm Criteria 10.5 E1 Framer/Formatter Control and Status Table 10-3. E1 Sync/Resync Criteria 10.5.1 Automatic Alarm Generation Table 10-4. E1 Alarm Criteria 10.6 Per-Channel Loopback 10.7 Error Counters 10.7.1 Line-Code Violation Counter (TR.LCVCR) Table 10-5 T1 Line Code Violation Counting Options Table 10-6. E1 Line-Code Violation Counting Options 0 BPVs 1 CVs Table 10-7. T1 Path Code Violation Counting Arrangements 10.7.3 Frames Out-of-Sync Count Register (TR.FOSCR) Table 10-8. T1 Frames Out-of-Sync Counting Arrangements 10.7.4 E-Bit Counter (TR.EBCR) 10.8 DS0 Monitoring Function 10.9 Signaling Operation Figure 10-2. Simplified Diagram of Receive Signaling Path 10.9.1 Processor-Based Receive Signaling 10.9.2 Hardware-Based Receive Signaling Figure 10-3. Simplified Diagram of Transmit Signaling Path 10.9.3 Processor-Based Transmit Signaling Table 10-9. Time Slot Numbering Schemes 10.9.4 Hardware-Based Transmit Signaling 10.10 Per-Channel Idle Code Generation Table 10-10. Idle-Code Array Address Mapping 10.10.1 Idle-Code Programming Examples 10.11 Channel Blocking Registers 10.12 Elastic Stores Operation 10.12.1 Receive Elastic Store 10.12.2 Transmit Elastic Store 10.12.3 Elastic Stores Initialization Table 10-11. Elastic Store Delay After Initialization 10.12.4 Minimum Delay Mode 10.13 G.706 Intermediate CRC-4 Updating (E1 Mode Only) + Figure 10-4. CRC-4 Recalculate Method 10.14 T1 Bit-Oriented Code (BOC) Controller 10.14.1 Transmit BOC 10.14.2 Receive BOC 10.15 Additional (Sa) and International (Si) Bit Operation (E1 Only) 10.15.1 Method 1: Internal Register Scheme Based on Double-Frame 10.15.2 Method 2: Internal Register Scheme Based on CRC4 Multiframe 10.16 Additional HDLC Controllers in T1/E1/J1 Transceiver 10.16.1 HDLC Configuration Table 10-12. HDLC Controller Registers 10.16.2 FIFO Control 10.16.3 HDLC Mapping 10.16.4 FIFO Information 10.16.5 Receive Packet-Bytes Available 10.17 Legacy FDL Support (T1 Mode) 10.17.1 Overview 10.17.2 Receive Section 10.17.3 Transmit Section 10.18 D4/SLC-96 Operation 10.19 Programmable In-Band Loop Code Generation and Detection 10.20 Line Interface Unit (LIU) 10.20.1 LIU Operation 10.20.2 Receiver Figure 10-5. Typical Monitor Application 10.20.3 Transmitter 10.21 MCLK Prescaler 01 11001 10.22 Jitter Attenuator 10.23 CMI (Code Mark Inversion) Option Figure 10-6. CMI Coding 2:1 1:1 0.1F 0.1F 0.1F 0.1F 0.01F 10F 10F Figure 10-8. E1 Transmit Pulse Template Figure 10-9. T1 Transmit Pulse Template Figure 10-10. Jitter Tolerance Figure 10-11. Jitter Tolerance (E1 Mode) Figure 10-12. Jitter Attenuation (T1 Mode) T1 MODE Figure 10-13. Jitter Attenuation (E1 Mode) Figure 10-14. Optional Crystal Connections 10.25 T1/E1/J1 TRANSCEIVER BERT FUNCTION 10.25.1 BERT Status 10.25.2 BERT Mapping Figure 10-15. Simplified Diagram of BERT in Network Direction Figure 10-16. Simplified Diagram of BERT in Backplane Direction 10.25.3 BERT Repetitive Pattern Set 10.25.4 BERT Bit Counter 10.25.5 BERT Error Counter 10.25.6 BERT Alternating Word-Count Rate 10.26 Payload Error-Insertion Function (T1 Mode Only) Table 10-14. Transmit Error-Insertion Setup Sequence 10.26.1 Number-of-Errors Registers Table 10-15. Error Insertion Examples 10.27 Programmable Backplane Clock Synthesizer 10.28 Fractional T1/E1 Support 10.29 T1/E1/J1 Transmit Flow Diagrams Figure 10-17. T1/J1 Transmit Flow Diagram T1 TRANSMIT FLOW DIAGRAM KEY - PIN - SELECTOR - REGISTER Page Figure 10-18. E1 Transmit Flow Diagram E1 TRANSMIT FLOW DIAGRAM KEY - PIN - SELECTOR - REGISTER 116 of 344 To Bipolar/NRZ coding Mux E1 TRANSMIT FLOW DIAGRAM 116 of 344 To Bipolar/NRZ coding Mux E1 TRANSMIT FLOW DIAGRAM 11 DEVICE REGISTERS Table 11-1. Register Address Map 11.1 Register Bit Maps 11.1.1 Global Ethernet Mapper Register Bit Map Table 11-2. Global Ethernet Mapper Register Bit Map 11.1.2 Arbiter Register Bit Map Table 11-3. Arbiter Register Bit Map 11.1.3 BERT Register Bit Map Table 11-4. BERT Register Bit Map 11.1.4 Serial Interface Register Bit Map Table 11-5. Serial Interface Register Bit Map Page 11.1.5 Ethernet Interface Register Bit Map Table 11-6. Ethernet Interface Register Bit Map 11.1.6 MAC Register Bit Map Table 11-7. MAC Indirect Register Bit Map Page Table 11-8. T1/E1/J1 Transceiver Register Bit Map (Active when CST = 0) Page Page Page Page Page Page Page Page 11.2 Global Register Definitions for Ethernet Mapper Page Page Page Page Page Page Page Page 11.3 Arbiter Registers 11.3.1 Arbiter Register Bit Descriptions 11.4 BERT Registers Page Page Page Page Page 11.5 Serial Interface Registers 11.5.1 Serial Interface Transmit and Common Registers Page Page Page Page Page Page Page 11.5.2 X.86 Registers Page 11.5.3 Receive Serial Interface Page Page Page Page Page Page Page Page Page Page Page Page 11.6 Ethernet Interface Registers 11.6.1 Ethernet Interface Register Bit Descriptions Page Page Page Page Page Page Page Page Page Page Page 11.6.2 MAC Registers Page Page Page Page Page Page Page Page Page Page Page Page Page Page 11.7 T1/E1/J1 Transceiver Registers Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page 12 FUNCTIONAL TIMING 12.1 Functional Serial I/O Timing Figure 12-1. Tx Serial Interface Functional Timing Figure 12-2. Rx Serial Interface Functional Timing Figure 12-3. Transmit Byte Sync Functional Timing Figure 12-4. Receive Byte Sync Functional Timing 12.2 MII and RMII Interfaces Figure 12-5. MII Transmit Functional Timing Figure 12-6. MII Transmit Half Duplex with a Collision Functional Timing Figure 12-7. MII Receive Functional Timing Figure 12-8. RMII Transmit Interface Functional Timing Figure 12-9. RMII Receive Interface Functional Timing 12.3 Transceiver T1 Mode Functional Timing RFSYNC RSYNC Figure 12-10. Receive-Side D4 Timing Figure 12-12. Receive-Side Boundary Timing (Elastic Store Disabled) Figure 12-13. Receive-Side 1.544MHz Boundary Timing (Elastic Store Enabled) Figure 12-14. Receive-Side 2.048MHz Boundary Timing (Elastic Store Enabled) RSER O TSSYNC RSYNC RCHCLK RCHBLK Figure 12-16. Transmit-Side ESF Timing TSSYNC FRAME# Figure 12-17. Transmit-Side Boundary Timing (with Elastic Store Disabled) Figure 12-18. Transmit-Side 1.544MHz Boundary Timing (Elastic Store Enabled) Figure 12-19. Transmit-Side 2.048MHz Boundary Timing (Elastic Store Enabled) TSYSCLK TSERI TSSYNC TSIG TCHCLK TCHBLK 12.4 E1 Mode Figure 12-20. Receive-Side Timing Figure 12-21. Receive-Side Boundary Timing (with Elastic Store Disabled) Figure 12-22. Receive-Side Boundary Timing, RSYSCLK = 1.544MHz (E-Store Enabled) RSERO RSERO RMSYNC RCHCLK RCHBLK Figure 12-24. G.802 Timing, E1 Mode Only TS # TSSYNC RCHCLK RCHBLK Figure 12-26. Transmit-Side Boundary Timing (Elastic Store Disabled) TCLKT TSERI TSIG Figure 12-27. Transmit-Side Boundary Timing, TSYSCLK = 1.544MHz (Elastic Store Enabled) TSYSCLK TSERI TSSYNC Figure 12-28. Transmit-Side Boundary Timing, TSYSCLK = 2.048MHz (Elastic Store Enabled) 13 OPERATING PARAMETERS ABSOLUTE MAXIMUM RATINGS Table 13-1. Recommended DC Operating Conditions Table 13-2. DC Electrical Characteristics 13.1 Thermal Characteristics Table 13-3. Thermal Characteristics Table 13-4. Theta-JA vs. Airflow 13.2 MII Interface Table 13-5. Transmit MII Interface Figure 13-1. Transmit MII Interface Timing Table 13-6. Receive MII Interface Figure 13-2. Receive MII Interface Timing 13.3 RMII Interface Table 13-7. Transmit RMII Interface Figure 13-3. Transmit RMII Interface Timing Table 13-8. Receive RMII Interface Figure 13-4. Receive RMII Interface Timing 13.4 MDIO Interface Table 13-9. MDIO Interface Figure 13-5. MDIO Interface Timing 13.5 Transmit WAN Interface Table 13-10. Transmit WAN Interface Figure 13-6. Transmit WAN Interface Timing 13.6 Receive WAN Interface Table 13-11. Receive WAN Interface Figure 13-7. Receive WAN Interface Timing 13.7 SDRAM Timing Table 13-12. SDRAM Interface Timing Figure 13-8. SDRAM Interface Timing Page Figure 13-9. Intel Bus Read Timing (MODEC = 00) Figure 13-10. Intel Bus Write Timing (MODEC = 00) Figure 13-11. Motorola Bus Read Timing (MODEC = 01) Figure 13-12. Motorola Bus Write Timing (MODEC = 01) 13.9 AC Characteristics: Receive-Side Table 13-14. AC Characteristics: Receive Side Figure 13-13. Receive-Side Timing DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 329 of 344 Figure 13-14. Receive-Side Timing, Elastic Store Enabled RMSYNC RSYSCLK Figure 13-15. Receive Line Interface Timing Figure 13-16. Receive Timing Delay RCLKO to BPCLK 13.11 AC Characteristics: Transmit Side Table 13-16. AC Characteristics: Transmit Side Figure 13-17. Transmit-Side Timing Figure 13-18. Transmit-Side Timing, Elastic Store Enabled Figure 13-19. Transmit Line Interface Timing 13.12 JTAG Interface Timing Table 13-17. JTAG Interface Timing Figure 13-20. JTAG Interface Timing Diagram 14 JTAG INFORMATION Figure 14-1. JTAG Functional Block Diagram 14.1 JTAG TAP Controller State Machine Description Update-DR Select-IR-Scan Capture-IR Shift-IR Exit1-IR Figure 14-2. TAP Controller State Diagram 14.2 Instruction Register Table 14-1. Instruction Codes for IEEE 1149.1 Architecture SAMPLE:PRELOAD BYPASS EXTEST CLAMP 14.3 JTAG ID Codes Table 14-2. ID Code Structure 14.4 Test Registers 14.4.1 Boundary Scan Register 14.4.2 Bypass Register 14.4.3 Identification Register 14.5 JTAG Functional Timing Figure 14-3. JTAG Functional Timing 15 PACKAGE INFORMATION 15.1 256-Ball BGA (27mm x 27mm) (56-G6004-001) 16 DOCUMENT REVISION HISTORY