DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver

 

 

 

 

 

 

 

NAME

PIN

TYPE

FUNCTION

 

SDATA[0]

W2

 

 

 

 

SDATA[1]

Y4

 

 

 

 

SDATA[2]

Y2

 

 

 

 

SDATA[3]

Y5

 

 

 

 

SDATA[4]

Y3

 

 

 

 

SDATA[5]

W5

 

 

 

 

SDATA[6]

V5

 

 

 

 

SDATA[7]

W6

 

 

 

 

SDATA[8]

V6

 

 

 

 

SDATA[9]

W4

 

 

 

 

SDATA[10]

V4

 

 

 

 

SDATA[11]

V2

 

 

 

 

SDATA[12]

V3

 

SDRAM Data Bus Bits 0 to 31: The 32 pins of the SDRAM data

 

 

SDATA[13]

V1

 

 

 

SDATA[14]

W3

 

bus are inputs for read operations and outputs for write operations.

 

 

SDATA[15]

W1

O

At all other times, these pins are high-impedance.

 

 

SDATA[16]

Y16

Note: All SDRAM operations are controlled entirely by the

 

 

 

 

 

SDATA[17]

Y17

 

 

 

 

 

 

DS33R11. No user programming for SDRAM buffering is required.

 

 

SDATA[18]

V18

 

 

SDATA[19]

Y19

 

 

 

 

SDATA[20]

V19

 

 

 

 

SDATA[21]

Y20

 

 

 

 

SDATA[22]

U19

 

 

 

 

SDATA[23]

W20

 

 

 

 

SDATA[24]

U20

 

 

 

 

SDATA[25]

T19

 

 

 

 

SDATA[26]

T20

 

 

 

 

SDATA[27]

Y18

 

 

 

 

SDATA[28]

W19

 

 

 

 

SDATA[29]

V17

 

 

 

 

SDATA[30]

W17

 

 

 

 

SDATA[31]

W16

 

 

 

 

SDA[0]

W14

 

 

 

 

SDA[1]

W12

 

SDRAM Address Bus 0 to 11: The 12 pins of the SDRAM address

 

 

SDA[2]

Y15

 

 

 

 

bus output the row address first, followed by the column address.

 

 

SDA[3]

W15

 

 

 

 

The row address is determined by SDA0 to SDA11 at the rising

 

 

SDA[4]

Y14

 

 

 

 

edge of clock. Column address is determined by SDA0-SDA9 and

 

 

SDA[5]

V13

O

 

 

SDA11 at the rising edge of the clock. SDA10 is used as an auto-

 

 

SDA[6]

W13

 

 

 

precharge signal.

 

 

SDA[7]

Y12

 

 

 

 

 

 

 

SDA[8]

V12

 

Note: All SDRAM operations are controlled entirely by the

 

 

SDA[9]

Y10

 

 

 

 

DS33R11. No user programming for SDRAM buffering is required.

 

 

SDA[10]

V14

 

 

 

 

 

 

 

SDA[11]

W11

 

 

 

 

SDMASK[0]

Y6

 

SDRAM Mask 0 through 3: When high, a write is done for that

 

 

SDMASK[1]

V7

O

 

 

byte. The least significant byte is SDATA7 to SDATA0. The most

 

 

SDMASK[2]

V16

 

 

 

significant byte is SDATA31 to SDATA24.

 

 

SDMASK[3]

V15

 

 

 

 

 

 

 

SDCLKO

Y8

O

SDRAM CLK Out: System clock output to the SDRAM. This clock

 

 

(4mA)

is a buffered version of SYSCLKI.

 

 

 

 

 

30 of 344

Page 30
Image 30
Maxim DS33R11 specifications Sdram Data Bus Bits 0 to 31 The 32 pins of the Sdram data