Maxim DS33R11 specifications TAP Controller State Diagram, Instruction Register

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver

Figure 14-2. TAP Controller State Diagram

1	Test Logic
	Reset
	0	1		1			1
0	Run Test/		Select			Select
	Idle		DR-Scan			IR-Scan
		1	0		1	0
			Capture DR			Capture IR

		0			0
	Shift DR		0		Shift IR	0
		1			1	1
		Exit DR	1		Exit IR
		0			0
	Pause DR		0	Pause IR		0
0		1		0	1
	Exit2 DR				Exit2 IR
		1			1
	Update DR			Update IR
	1	0		1	0

14.2 Instruction Register

The instruction register contains a shift register as well as a latched parallel output and is 3 bits in length. When the TAP controller enters the Shift-IR state, the instruction shift register is connected between JTDI and JTDO. While in the Shift-IR state, a rising edge on JTCLK with JTMS LOW will shift the data one stage towards the serial output at JTDO. A rising edge on JTCLK in the Exit1-IR state or the Exit2-IR state with JTMS HIGH will move the controller to the Update-IR state. The falling edge of that same JTCLK will latch the data in the instruction shift register to the instruction parallel output. Instructions supported by the DS26521 and its respective operational binary codes are shown in Table 14-1.

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