Time Slot Numbering Schemes, 10.9.3.2 E1 Mode | Maxim DS33R11

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver

10.9.3.2 E1 Mode

In E1 mode, TS16 carries the signaling information. This information can be in either CCS (common channel signaling) or CAS (channel associated signaling) format. The 32 time slots are referenced by two different channel number schemes in E1. In “Channel” numbering, TS0–TS31 are labeled channels 1 through 32. In “Phone Channel” numbering, TS1–TS15 are labeled channel 1 through channel 15 and TS17–TS31 are labeled channel 15 through channel 30. In E1 CAS mode, the CAS signaling alignment/alarm byte can be sourced from the transmit signaling registers along with the signaling data.

Table 10-9. Time Slot Numbering Schemes

TS	0	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15	16	17	18	19	20	21	22	23	24	25	26	27	28	29	30	31
Channel	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15	16	17	18	19	20	21	22	23	24	25	26	27	28	29	30	31	32
Phone		1	2	3	4	5	6	7	8	9	10	11	12	13	14	15		16	17	18	19	20	21	22	23	24	25	26	27	28	29	30
Channel

10.9.4 Hardware-Based Transmit Signaling

In hardware-based mode, signaling data is input through the TSIG pin. This signaling PCM stream is buffered and inserted to the data stream being input at the TSERI pin.

Signaling data can be inserted on a per-channel basis by the transmit hardware-signaling channel-select (THSCS) function. The user has the ability to control which channels are to have signaling data from the TSIG pin inserted into them on a per-channel basis. See Section 10.2 for details on using this per-channel (THSCS) feature. The signaling insertion capabilities of the framer are available whether the transmit-side elastic store is enabled or disabled. If the elastic store is enabled, the backplane clock (TSYSCLK) can be either 1.544MHz or 2.048MHz. Also, if the elastic is enabled in conjunction with transmit hardware signaling, CCR3.7 must be set = 0.

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Maxim DS33R11 Time Slot Numbering Schemes, Hardware-Based Transmit Signaling, 10.9.3.2 E1 Mode, Channel Phone

Contents

Part Temp Range PIN-PACKAGE DS33R11 Table of Contents Integrated T1/E1/J1 Transceiver Device Registers Operating Parameters List of Figures 308 List of Tables Description Page General X.86 Link Access Protocol for SONET/SDH Ethernet MappingMicroprocessor Interface Hdlc Ethernet Mapping Sdram Interface Committed Information Rate CIR ControllerMAC Interface Clock Synthesizer T1/E1/J1 Line InterfaceJitter Attenuator TDM Bus 12 T1/E1/J1 Framer Test and Diagnostics T1-Related Telecommunications Specifications Specifications Compliance Ethernet-to-WAN Extension With or Without Framing BOC B8ZSCRC ESF Major Operating Modes Bert Clad Ttip Transmit Framer MUX TringRtip Rring MUX JTAG2 Transmit Serial Port Packet HDLC/X.86 CIR Controller Jtag Host Interface Clock Receive and Transmit T1/E1/J1 LIU Loopback Sync Framer Data Sync Signaling Tseri Tsig Sync Rsync Rmsync Rfsync Internal Rdata Signals Rchclk FromRlink Rlclk Name PIN Type Function Microprocessor Port Pin Functional Description Detailed Pin DescriptionsIOZ Name PIN Type Function Read Data Strobe Intel Mode The DS33R11 drives the data busChip Select for Protocol Conversion Device This pin must be Receive Data 0 through 3 MII Four bits of received data Name PIN Type Function MII/RMII PHY PortReceive Data 0 through 1 Rmii Two bits of received data Transmit Data 0 through 3MII TXD 30 is presented Reference Clock Rmii and MII When in Rmii mode, all signalsTransmit Data 0 through 1RMII Two bits of data TXD Reference Clock Output Rmii and MII a derived clock output Sdram Interface Name PIN Type Function PHY Management BUSSdcs Sdram Data Bus Bits 0 to 31 The 32 pins of the Sdram data T1/E1/J1 Transmit Framer Interface Name PIN Type Function T1/E1/J1 Analog Line Interface T1/E1/J1 Receive Framer Interface Ethernet Mapper Transmit Serial Interface Receive Frame Sync Pre Receive Elastic Store for T1/E1/J1 Receive System Clock for the Transceiver 1.544MHzReceive Multiframe Sync for the T1/E1/J1 Transceiver An T1/E1/J1 FRAMER/LIU Interim Signals Transmit Positive-Data Output Updated on the rising edge Transmit Negative-Data Output Updated on the rising edgeTransmit Elastic Store Output Updated on the rising edge Transmit Clock Output from the T1/E1/J1 Framer Buffered Mode Control for Processor Interface Name PIN Type Function Hardware and Status PinsT1/E1/J1 Receive Signaling-Freeze Output Set high when Queue Overflow for Ethernet Mapper This pin goes high when Name PIN Type Function System Clocks Name PIN Type Function Jtag Interface Receive Analog Positive Supply Connect to 3.3V power supply Name PIN Type Function Power SuppliesReceive Analog Signal Ground Connect to the common supply Transmit Analog Signal Ground Connect to the common supply Ball BGA Pinout Functional Description Read-Write/Data Strobe Modes Processor InterfaceClear on Read Interrupt and Pin Modes Clocking Options for the Ethernet Interface Ethernet Mapper ClocksRmiimiis Speed DCE/ DTE Refclko Rxclk PIN Output Input Txclk Ethernet MAC T1/E1/J1Bert Refclk Arbiter Serial Interface Clock Modes Ethernet Interface Clock Modes Reset Functions Resets and Low Power ModesReset Function Location Comments Global Resources Initialization and ConfigurationPer-Port Resources Example Device Initialization Sequence Device Interrupts Pin Drawing Legend Status Registers Interrupt Information RegistersInformation Registers Serial Interface Connections and Queues Arbiter Registers Related to Connections and QueuesRegister Function Flow Control Type ModeOptions for Flow Control Full Duplex Flow Control Host-Managed Flow Control Half Duplex Flow Control Ieee 802.3 Ethernet Frame Ethernet Interface Port Register Name Function Registers Related to Setting the Ethernet Port DTE and DCE Mode Configured as DTE Connected to an Ethernet PHY in MII Mode Ethernet MAC DS33R11 Configured as a DCE in MII Mode MAC Status Registers MAC Control RegistersAddress Register Description Rmii Mode MII Mode Options Bert in the Ethernet Mapper Bert FeaturesPHY MII Management Block and Mdio Interface Receive Pattern Detection Receive Data InterfacePrbs Synchronization Pattern Monitoring Repetitive Pattern SynchronizationPattern Generation Performance Monitoring Update Error InsertionTransmit Packet Processor Receive Packet Processor 11. Hdlc Encapsulation of MAC Frame 12. Laps Encoding of MAC Frames Concept 19 X.86 Encoding and Decoding 13. X.86 Encapsulation of the MAC frame Page Committed Information Rate Controller T1/E1/J1 Clock Map 10.1 T1/E1/J1 Clocks Per-Channel Operation T1/E1/J1 Transmit Clock Source10.3 T1/E1/J1 Transceiver Interrupts TCSS1 TCSS0 Transmit Clock Source 10.4.1 T1 Transmit Transparency 10.4 T1 Framer/Formatter Control and StatusAIS-CI and RAI-CI Generation and Detection Alarm SET Criteria Clear Criteria T1 Alarm Criteria10.4.3 T1 Receive-Side Digital-Milliwatt Code Generation E1 Sync/Resync Criteria 10.5 E1 Framer/Formatter Control and StatusFrame or Sync Criteria Resync Criteria Multiframe Level ITU Spec Automatic Alarm Generation E1 Alarm CriteriaAlarm SET Criteria Clear Criteria ITU Specification Per-Channel Loopback T1 Line Code Violation Counting Options Error CountersE1 Line-Code Violation Counting Options Line-Code Violation Counter TR.LCVCR T1 Path Code Violation Counting Arrangements Framing ModePath Code Violation Count Register TR.PCVCR Counted Frames Out-of-Sync Count Register TR.FOSCR T1 Frames Out-of-Sync Counting ArrangementsBit Counter TR.EBCR 10.8 DS0 Monitoring Function Processor-Based Receive Signaling Signaling OperationChange-of-State Receive Signaling Reinsertion at Rsero Hardware-Based Receive SignalingForce Receive Signaling All Ones Receive Signaling Freeze 10.9.3.1 T1 Mode Processor-Based Transmit Signaling 10.9.3.2 E1 Mode Hardware-Based Transmit SignalingTime Slot Numbering Schemes Channel Phone 10. Idle-Code Array Address Mapping Per-Channel Idle Code GenerationBits 0 to 5 of Iaar Maps to Channel Example Idle-Code Programming Examples 10.12.1.2 E1 Mode 10.12.1.1 T1 ModeChannel Blocking Registers Elastic Stores Operation Minimum Delay Mode 11. Elastic Store Delay After InitializationInitialization Register BIT Delay Transmit Elastic Store CRC-4 Recalculate Method 10.13 G.706 Intermediate CRC-4 Updating E1 Mode Only Transmit BOC 10.14 T1 Bit-Oriented Code BOC ControllerReceive BOC Transmit a BOC Method 1 Internal Register Scheme Based on Double-Frame Additional Sa and International Si Bit Operation E1 OnlyMethod 2 Internal Register Scheme Based on CRC4 Multiframe Additional Hdlc Controllers in T1/E1/J1 Transceiver Hdlc Configuration 12. Hdlc Controller Registers Hdlc Mapping Fifo ControlRegister Channels Receive Packet-Bytes Available Fifo InformationReceive Hdlc Code Example Overview Legacy FDL Support T1 ModeReceive Section Transmit Section 10.18 D4/SLC-96 Operation Programmable In-Band Loop Code Generation and Detection LIU Operation Line Interface Unit LIUReceiver Receive G.703 Synchronization Signal E1 Mode Receive Level Indicator and Threshold InterruptMonitor Mode T1/E1 Transmit G.703 Synchronization Signal E1 Mode Transmit BPV Error InsertionTransmitter Transmit Short-Circuit Detector/Limiter CMI Code Mark Inversion Option Mclk PrescalerClock Data CMI Specification Recommended Value 13. Transformer SpecificationsRecommended Circuits -7. Basic Interface DS33R11 E1 Transmit Pulse Template 10. Jitter Tolerance E1 Mode T1 Mode Bert Mapping Bert StatusXtald Mclk 15. Simplified Diagram of Bert in Network Direction Bert Repetitive Pattern Set Bert Error CounterBert Bit Counter Bert Alternating Word-Count Rate 14. Transmit Error-Insertion Setup Sequence Payload Error-Insertion Function T1 Mode Only15. Error Insertion Examples Number-of-Errors Registers Fractional T1/E1 Support Programmable Backplane Clock Synthesizer T1 Transmit 114 E1 Transmit 116 E1 Transmit Flow Diagram Mapper Chip Global Arbiter Bert Serial Ethernet Register Address MapInterfac Port Select Registers Interface Transceiver Global Ethernet Mapper Register Bit Map Register Bit MapsGlobal Ethernet Mapper Register Bit Map Name Bert Register Bit Map Arbiter Register Bit MapArbiter Register Bit Map Bert Register Bit Map Serial Interface Register Bit Map Serial Interface Register Bit Map 114h Ethernet Interface Register Bit Map Ethernet Interface Register Bit Map MAC Register Bit Map MAC Indirect Register Bit Map 200h 019 T1/E1/J1 Transceiver Register Bit Map Active when CST = 01A 035 050 06A 085 0AB 0AA0AC 0AD 0CB 0CA0CC 0CD 0DD 0DC0DE 0DF GL.IDRL Global Register Definitions for Ethernet MapperGL.IDRH GL.BLR GL.CR1 GL.SRCALS GL.RTCALGL.LIE GL.SIE GL.LISGL.SIS GL.TRQIS GL.TRQIEGL.BIE GL.CON1 GL.BIS GL.BISTEN GL.C1QPR GL.SDMODE1 GL.BISTPF GL.SDMODEWS GL.SDMODE2GL.SDRFTC Arbiter Register Bit Descriptions Arbiter RegistersAR.RQSC1 AR.TQSC1 BCR Bert RegistersBert Control Register 80h Bpchr Bpclr BSPB1R BSPB0RBSPB2R BSPB3R BSR Teicr Bsrie Bsrl RBECB1R RBECB0RRBECR2 RBCB0 RBCB2 RBCB1RBCB3 Serial Interface Transmit and Common Registers Serial Interface RegistersLI.TSLCR LI.RSTPD LI.TPPCL LI.LPBK LI.TEPLC LI.TIFGC Cleanup routine Transmit Errored Packet High Control RegisterLI.TEPHC 0C7h LI.TPPSRL LI.TPPSRLI.TPPSRIE LI.TPCR1 LI.TPCR0LI.TPCR2 LI.TBCR1 LI.TBCR0LI.TBCR2 LI.TBCR3 LI.THPMUS LI.THPMUU LI.TX86EDE 11.5.2 X.86 RegistersLI.TRX86A LI.TRX8C LI.CIR LI.TRX86SAPIL LI.RSLCR Receive Serial InterfaceLI.RPPCL LI.RMPSCH LI.RMPSCLLI.RPPSR Receive Packet Processor Status Register Latched LI.RPPSRL105h Repl Rapl Ripdl Rspdl Rlpdl Repcl Rapcl Rspcl LI.RPPSRIE Receive Packet Processor Status Register Interrupt Enable106h Repie Rapie Ripdie Rspdie Rlpdie Repcie Rapcie Rspcie LI.RPCB1 LI.RPCB0LI.RPCB2 LI.RFPCB1 LI.RFPCB0LI.RFPCB2 LI.RAPCB1 LI.RAPCB0LI.RAPCB2 LI.RSPCB1 LI.RSPCB0LI.RSPCB2 LI.RBC1 LI.RBC0LI.RBC2 LI.RBC3 LI.RAC1 LI.RAC0LI.RAC2 LI.RAC3 LI.RHPMUS LI.RHPMUULI.RX86S LI.TQLT LI.RX86LSIELI.TQHT 126h LI.TQTIELI.TQCTLS 127h Ethernet Interface Register Bit Descriptions Ethernet Interface RegistersSU.MACRADL SU.MACRADH SU.MACRD2 SU.MACRD1SU.MACRD3 SU.MACWD0 SU.MACWD2 SU.MACWD1SU.MACWD3 SU.MACAWL SU.MACRWC SU.MACAWH SU.GCR SU.LPBK Transmit Frame Resend Control SU.TFRC151h Ncfq Tprhbc Tprcb SU.TFSH SU.TFSL SU.RFSB1 SU.RFSB0SU.RFSB2 157h SU.RFSB3MCF SU.RMFSRH SU.RMFSRLSU.RQLT SU.RQHT SU.QCRLS SU.QRIE Receive Frame Rejection Control SU.RFRC15Eh Ucfr Cfrr Lerr Crcerr DBR Miier BFR SU.MACCR MAC Registers Bit Random Number Generator Bits Used SU.MACMIIA SU.MACMIID SU.MACFCR SU.MMCCTRL MAC Reserved Control Register Reserved010Ch indirect 010Dh 0111h 0110h indirect0112h 0113h MAC All Frames Received Counter SU.RxFrmCtr0200h indirect 0201h MAC Frames Received OK Counter SU.RxFrmOkCtr0204h indirect 0205h MAC All Frames Transmitted Counter SU.TxFrmCtr0300h indirect 0301h MAC All Bytes Transmitted Counter SU.TxBytesCtr0308h indirect 0309h MAC Bytes Transmitted OK Counter SU.TxBytesOkCtr030Ch indirect 030Dh MAC Transmit Frame Under Run Counter SU.TxFrmUndr0334h indirect 0335h MAC All Frames Aborted Counter SU.TxBdFrmCtr0338h indirect 0339h Effect On Output Pins Master Mode Register11.7 T1/E1/J1 Transceiver Registers TR.MSTRREG Bit 6 Rsync Mode Select 2 RSMS2 Configuration RegisterTR.IOCR1 Bit 1 Tsync I/O Select Tsio 0 = Tsync is an input TR.IOCR2 OOF2 OOF1 TR.T1RCR1 Bit 5 Receive B8ZS Enable RB8ZS Bit 6 Receive Frame Mode Select RFM 0 = D4 framing modeBit 1 Receive Japanese CRC6 Enable RJC TR.T1RCR2 TR.T1TCR1 TR.T1TCR2 Bit 7 Transmit B8ZS Enable TB8ZSTB8ZS TSLC96 Tzse FBCT2 FBCT1 TD4YM TB7ZS TR.SSIE1 T1 Mode Bit 2 Transmit Frame Mode Select TFM 0 = D4 framing modeTR.T1CCR1 T1 Common Control Register Software Signaling Insertion Enable TR.SSIE1 E1 ModeTR.SSIE2 E1 Mode Lcaw TR.SSIE3 E1 ModeTR.SSIE4 TR.T1RDMR2 TR.T1RDMR1TR.T1RDMR3 TR.INFO1 TR.IDR 11h TR.INFO2Bits 0 3 Receive Level Bits RL0 to RL3. Real-time bits RL3 RL2 RL1 RL0 TR.IIR1 TR.INFO3TR.IIR2 TR.SR1 Ilut Timer Rscos Jalt Lrcl Tcle Tocd LolitcStatus Register 16h Interrupt Mask Register TR.IMR117h Bit 7 Input Level Under Threshold Ilut 0 = interrupt masked 18h TR.SR2Ryelc RUA1C Frclc Rlosc 19h TR.IMR2Bit 0 Receive Loss-of-Sync Condition Rlos 1Ah TR.SR3Lspare LDN LUP Lotc Lorc V52LNK Rdma RRA TR.IMR3 1Ch TR.SR4RAIS-CI Rsao Rsaz TMF TAF RMF Rcmf RAF Bit 2 Receive Multiframe Event RMF 1Dh TR.IMR4Bit 7 Receive AIS-CI Event RAIS-CI Bit 3 Transmit Align Frame Event TAF 0 = interrupt masked 1Eh TR.SR5Tesf Tesem Tslip Resf Resem Rslip 1Fh TR.IMR5 Hdlc #1 Status Register TR.SR6, TR.SR7Hdlc #2 Status Register 20h, 22h TR.IMR6, TR.IMR7 PS2 PS1 PS0 TR.INFO5, TR.INFO6TR.INFO4 TR.IMR8 TR.SR8 26h TR.SR9Bbed Bbco BEC0 BRA1 BRA0 Brlos Bsync TR.IMR9 Per-Channel Pointer Register TR.PCPR28h Rsaoics Rsrcs Rfcs Brcs Thscs Peics Tfcs Btcs TR.PCDR2 TR.PCDR1TR.PCDR3 TR.PCDR4 TR.H1RC, TR.H2RC TR.INFO7Hdlc #1 Receive Control Hdlc #2 Receive Control 31h, 32h TR.E1RCR2 TR.E1RCR1 TR.E1TCR1 TR.BOCC TR.E1TCR2RBF1 RBF0 MSB LSB TR.RSINFO1, TR.RSINFO2, TR.RSINFO3, TR.RSINFO4TR.RSCSE1, TR.RSCSE2, TR.RSCSE3, TR.RSCSE4 TR.SIGCR Signaling Control RegisterGrsre RFE RFF Rccs Tccs Frsao Bit 5 Error-Counter Update Select Ecus Error-Counter Configuration RegisterBit 4 Error-Accumulation Mode Select Eams Bit 2 Pcvcr Fs-Bit Error-Report Enable Fsbe TR.LCVCR2 TR.LCVCR1TR.PCVCR1 TR.PCVCR2 TR.FOSCR2 TR.FOSCR1TR.EBCR1 TR.EBCR2 Loopback Control Register TR.LBCR4Ah Liuc LLB RLB PLB FLB TR.PCLR2 TR.PCLR1TR.PCLR3 TR.PCLR4 Elastic Store Control Register TR.ESCR4Fh Tesalgn Tesr Tesmdm Tese Resalgn Resr Resmdm Rese TR.TS1 to TR.TS16 Transmit Signaling Registers E1 Mode, CAS Format50h to 5Fh Transmit Signaling Registers E1 Mode, CCS Format TR.TS1 to TR.TS12 Transmit Signaling Registers T1 Mode, ESF Format50h to 5Bh CH2-A CH2-B Transmit Signaling Registers T1 Mode, D4 FormatCH1-A CH1-B CH4-A CH4-B Receive Signaling Registers T1 Mode, D4 Format Receive Signaling Registers T1 Mode, ESF FormatTR.RS1 to TR.RS12 60h to 6Bh Receive Signaling Registers E1 Mode, CCS Format Receive Signaling Registers E1 Mode, CAS FormatTR.RS1 to TR.RS16 60h to 6Fh TCSS1 TCSS0 TR.CCR1 BPCS1 BPCS0 TR.CCR2TR.CCR3 RLT3 RLT2 RLT1 RLT0 TR.CCR4TR.TDS0SEL TR.RDS0SEL TR.TDS0MTR.RDS0M TR.LIC1 Network Mode GC5 GC4 GC3 GC2 GC1 GC0 Bit 6 Automatic Gain Control Enable AgceTR.TLBC T1, Impedance Match Off 79h TR.LIC2ETS Lirst Ibpv TUA1 Jamux Scld Clds Bit 7 E1/T1 Select ETS MM1 MM0 TR.LIC3 MPS1 MPS0 Jamux TR.LIC4Mclk MPS1 MPS0 Jamux TT1 TT0 Gric Gtic Function TR.IAARTR.PCICR TR.TCICE1 TR.TCICE3 TR.TCICE2TR.TCICE4 TR.RCICE1 TR.RCICE3 TR.RCICE2TR.RCICE4 TR.RCBR1 TR.RCBR3 TR.RCBR2TR.RCBR4 TR.TCBR2 TR.TCBR1TR.TCBR3 TR.TCBR4 Hdlc #1 Transmit Control TR.H1TC, TR.H2TCHdlc #2 Transmit Control 90h, A0h TFLWM2 TFLWM1 TFLWM0 TR.H1FC, TR.H2FCRFHWM2 RFHWM1 RFHWM0 A2h, A3h, A4h, A5h Register Name TR.H1RCS1, TR.H1RCS2, TR.H1RCS3, TR.H1RCS4Bit 3 Receive Hdlc Channel Select Bit Bit 2 Receive Hdlc Channel Select Bit Hdlc # 1 Receive Time Slot Bits/Sa Bits Select TR.H1RTSBS, TR.H2RTSBSHdlc # 2 Receive Time Slot Bits/Sa Bits Select 96h, A6h RCB8SE RCB7SE RCB6SE RCB5SE RCB4SE RCB3SE RCB2SE RCB1SE A7h, A8h, A9h, AAh Register Name TR.H1TCS1, TR.H1TCS2, TR.H1TCS3, TR.H1TCS4Bit 3 Transmit Hdlc Channel Select Bit Bit 2 Transmit Hdlc Channel Select Bit TR.H1RPBA, TR.H2RPBA TR.H1TTSBS, TR.H2TTSBS TR.H1RF, TR.H2RF TR.H1TF, TR.H2TF TR.IBCC TR.H1TFBA, TR.H2TFBATC1 TC0 RUP2 RUP1 RUP0 TR.TCD2 TR.TCD1Transmit Code Definition Register B8h Receive Up-Code Definition Register TR.RUPCD2BAh Receive Down-Code Definition Register TR.RDNCD1BBh TR.RDNCD2 In-Band Receive Spare Control Register TR.RSCCBDh RSC2 RSC1 RSC0 TR.RSCD2 TR.RSCD1 Receive FDL Register TR.RFDL TR.BOCC.4 =C0h RBOC5 RBOC4 RBOC3 RBOC2 RBOC1 RBOC0 TR.RFDLM1, TR.RFDLM2 TR.TFDL Receive Align Frame Register TR.RAFC6h TR.RNAF Received Si Bits of the Align Frame TR.RSiAFC8h TR.RSiNAF TR.RRA Received Sa5 Bits TR.RSa5CCh TR.RSa6 Received Sa7 Bits TR.RSa7CEh TR.RSa8 TR.TNAF TR.TAF Transmit Si Bits of the Align Frame TR.TSiAFD2h TR.TSiNAF TR.TRA Transmitted Sa5 Bits TR.TSa5D6h TR.TSa6 Transmit Sa7 Bits TR.TSa7D8h TR.TSa8 TR.BAWC TR.TSACR TR.BRP2 TR.BRP1TR.BRP3 TR.BRP4 PS1 PS0 TR.BC1 EIB2 EIB1 EIB0 TR.BC2RPL3 RPL2 RPL1 RPL0 TR.BBC2 TR.BBC1TR.BBC3 TR.BBC4 EC7 EC6 EC5 EC4 EC3 EC2 EC1 EC0 TR.BEC1TR.BEC2 EC9 EC8 TR.BIC ER3 ER2 ER1 ER0 TR.ERC TR.NOE1 Number-of-ErrorsECh TR.NOE2 TR.NOEL2 TR.NOEL1 Tx Serial Interface Functional Timing Functional Serial I/O Timing MII and Rmii Interfaces Transmit Byte Sync Functional Timing MII Transmit Half Duplex with a Collision Functional Timing FRAME# RSYNC1 Rfsync RSYNC2 Rsync FRAME# Rfsync RSYNC1 Rsync 2 RSYNC3 Rchclk RCHBLK1 Rsync RfsyncRchclk Rchblk Rchclk RCHBLK4 Rsysclk Rser O Tchclk Tchblk FRAME# TSYNC1 Tssync Tsync TSYNC3 Tchclk Tchblk 2,3 FRAME# Rfsync Rsync 12.4 E1 Mode RSYNC2 Rmsync RSYNC3 Rchclk Rchblk Rsysclk RseroRmsync Rsync Rchclk RCHBLK3 FRAME# TSYNC1 Tssync Rsync Tsync Rchclk Tchclk Rchblk TchblkTSYNC2 Tssync Tchclk Tchblk 26. Transmit-Side Boundary Timing Elastic Store Disabled 312 Parameter Symbol Conditions MIN TYP MAX Units DC Electrical CharacteristicsRecommended DC Operating Conditions Theta-JA vs. Airflow Thermal Characteristics -3. Thermal CharacteristicsParameter MIN TYP MAX AIR Flow THETA-JA MII Interface Transmit MII Interface Parameter Symbol10Mbps 100Mbps MIN TYP MAX Receive MII Interface Timing Receive MII Interface Transmit Rmii Interface Timing Rmii Interface Transmit Rmii Interface Receive Rmii Interface Timing Receive Rmii Interface Mdio Interface Parameter Symbol MIN TYP MAX UnitsMDC Mdio Tclke Tsero Tden Tbsync Transmit WAN Interface 10. Transmit WAN Interface Rclki Rseri Rden Rbsync Receive WAN Interface 11. Receive WAN Interface 100 MHz Sdram Timing 12. Sdram Interface Timing RAS, Scas SdataSWE, Sdcs SDA, SBA Parameter Symbol MIN TYP MAX Units Intel Bus Read Timing Modec = 11. Motorola Bus Read Timing Modec = RMSYNC, Rsync RCHBLK, Rfsync Rfsync / Rmsync Rsero / Rdata / Rsig See Note Rsero / RsigRchblk Rmsync Rsync 15. Receive Line Interface Timing Delay Rclko to Bpclk 16. Receive Timing Delay Rclko to Bpclk TSERI, TSIG, TDATA, TPOSI, Tnegi Parameter Symbol Conditions MIN TYP E1 MAX Units 17. Transmit-Side Timing 18. Transmit-Side Timing, Elastic Store Enabled Jtag Interface Timing 17. Jtag Interface Timing 20. Jtag Interface Timing Diagram Jtag Information Jtag TAP Controller State Machine Description Update-IR Update-DRSelect-IR-Scan Capture-IR Instruction Register TAP Controller State Diagram Instruction Selected Register Instruction Codes Instruction Codes for Ieee 1149.1 Architecture Test Registers Jtag ID Codes ID Code StructureBoundary Scan Register Bypass Register Bypass Idcode State Jtag Functional Timing 15.1 256-Ball BGA 27mm x 27mm 56-G6004-001 Package Information Revision Description Document Revision History