DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver

Register Name:

TR.PCDR1

Register Description:

Per-Channel Data Register 1

Register Address:

29h

Bit #

Name

Default

7

6

5

4

3

2

1

0

CH8

CH7

CH6

CH5

CH4

CH3

CH2

CH1

Register Name:

TR.PCDR2

Register Description:

Per-Channel Data Register 2

Register Address:

2Ah

Bit #

Name

Default

7

6

5

4

3

2

1

0

CH16

CH15

CH14

CH13

CH12

CH11

CH10

CH9

Register Name:

TR.PCDR3

Register Description:

Per-Channel Data Register 3

Register Address:

2Bh

Bit #

Name

Default

7

6

5

4

3

2

1

0

CH24

CH23

CH22

CH21

CH20

CH19

CH18

CH17

Register Name:

TR.PCDR4

Register Description:

Per-Channel Data Register 4

Register Address:

2Ch

Bit #

Name

Default

7

6

5

4

3

2

1

0

CH32

CH31

CH30

CH29

CH28

CH27

CH26

CH25

See Section 10.2 for a general overview of per-channel operation. See Section 10.10 for more information on per- channel idle code generation. See Section 10.6 for more information on per-channel loopback operation.

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Maxim DS33R11 specifications TR.PCDR1, TR.PCDR2, TR.PCDR3, TR.PCDR4