Maxim DS33R11 LIST OF FIGURES

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
6 of 344
LIST OF FIGURES
Figure 3-1. Ethernet-to-WAN Extension (With or Without Framing) .........................................................................17
Figure 6-1. Main Block Diagram................................................................................................................................20
Figure 6-2. Block Diagram of T1/E1/J1 Transceiver................................................................................................. 21
Figure 6-3. Receive and Transmit T1/E1/J1 LIU....................................................................................................... 22
Figure 6-4. Receive and Transmit T1/E1/J1 Framer................................................................................................. 23
Figure 6-5. T1/E1/J1 Backplane Interface................................................................................................................. 24
Figure 7-1. 256-Ball BGA Pinout............................................................................................................................... 40
Figure 9-1. Clocking for the DS33R11....................................................................................................................... 44
Figure 9-2. Device Interrupt Information Flow Diagram............................................................................................ 49
Figure 9-3. Flow Control Using Pause Control Frame.............................................................................................. 55
Figure 9-4. IEEE 802.3 Ethernet Frame.................................................................................................................... 56
Figure 9-5. Configured as DTE Connected to an Ethernet PHY in MII Mode........................................................... 58
Figure 9-6. DS33R11 Configured as a DCE in MII Mode.......................................................................................... 59
Figure 9-7. RMII Interface.......................................................................................................................................... 61
Figure 9-8. MII Management Frame.......................................................................................................................... 62
Figure 9-9. PRBS Synchronization State Diagram.................................................................................................... 63
Figure 9-10. Repetitive Pattern Synchronization State Diagram............................................................................... 64
Figure 9-11. HDLC Encapsulation of MAC Frame.................................................................................................... 67
Figure 9-12. LAPS Encoding of MAC Frames Concept............................................................................................ 68
Figure 9-13. X.86 Encapsulation of the MAC frame.................................................................................................. 69
Figure 10-1. T1/E1/J1 Clock Map.............................................................................................................................. 72
Figure 10-2. Simplified Diagram of Receive Signaling Path...................................................................................... 82
Figure 10-3. Simplified Diagram of Transmit Signaling Path..................................................................................... 84
Figure 10-4. CRC-4 Recalculate Method.................................................................................................................. 90
Figure 10-5. Typical Monitor Application................................................................................................................. 101
Figure 10-6. CMI Coding......................................................................................................................................... 103
Figure 10-7. Basic Interface.....................................................................................................................................104
Figure 10-8. E1 Transmit Pulse Template............................................................................................................... 105
Figure 10-9. T1 Transmit Pulse Template............................................................................................................... 105
Figure 10-10. Jitter Tolerance .................................................................................................................................106
Figure 10-11. Jitter Tolerance (E1 Mode)................................................................................................................106
Figure 10-12. Jitter Attenuation (T1 Mode)..............................................................................................................107
Figure 10-13. Jitter Attenuation (E1 Mode)............................................................................................................. 107
Figure 10-14. Optional Crystal Connections ...........................................................................................................108
Figure 10-15. Simplified Diagram of BERT in Network Direction............................................................................ 109
Figure 10-16. Simplified Diagram of BERT in Backplane Direction........................................................................ 109
Figure 10-17. T1/J1 Transmit Flow Diagram........................................................................................................... 113
Figure 10-18. E1 Transmit Flow Diagram................................................................................................................ 115
Figure 12-1. Tx Serial Interface Functional Timing .................................................................................................300
Figure 12-2. Rx Serial Interface Functional Timing................................................................................................. 300
Figure 12-3. Transmit Byte Sync Functional Timing ...............................................................................................301
Figure 12-4. Receive Byte Sync Functional Timing ................................................................................................301
Figure 12-5. MII Transmit Functional Timing........................................................................................................... 301
Figure 12-6. MII Transmit Half Duplex with a Collision Functional Timing.............................................................. 302
Figure 12-7. MII Receive Functional Timing............................................................................................................ 302
Figure 12-8. RMII Transmit Interface Functional Timing......................................................................................... 302
Figure 12-9. RMII Receive Interface Functional Timing.......................................................................................... 303
Figure 12-10. Receive-Side D4 Timing................................................................................................................... 303
Figure 12-11. Receive-Side ESF Timing................................................................................................................. 303
Figure 12-12. Receive-Side Boundary Timing (Elastic Store Disabled)..................................................................304
Figure 12-13. Receive-Side 1.544MHz Boundary Timing (Elastic Store Enabled)................................................. 304
Figure 12-14. Receive-Side 2.048MHz Boundary Timing (Elastic Store Enabled)................................................. 305
Figure 12-15. Transmit-Side D4 Timing.................................................................................................................. 305
Figure 12-16. Transmit-Side ESF Timing................................................................................................................ 306
Figure 12-17. Transmit-Side Boundary Timing (with Elastic Store Disabled)......................................................... 306
Figure 12-18. Transmit-Side 1.544MHz Boundary Timing (Elastic Store Enabled)................................................ 307