DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver

Figure 13-18. Transmit-Side Timing, Elastic Store Enabled

tR

TSYSCLK

TSERI

TCHCLK

TCHBLK

TSSYNC

 

tF

 

tSU

t D3

tHD

 

tD3

 

tHD

 

tSU

 

tSP

tSL

tSH

NOTE 1: TSERI IS ONLY SAMPLED ON THE FALLING EDGE OF TSYSCLK WHEN THE TRANSMIT-SIDE ELASTIC STORE IS ENABLED.

NOTE 2: TCHCLK AND TCHBLK ARE SYNCHRONOUS WITH TSYSCLK WHEN THE TRANSMIT-SIDE ELASTIC STORE IS ENABLED.

Figure 13-19. Transmit Line Interface Timing

TDCLKO

TPOSO, TNEGO

 

t DD

tR

tF

TDCLKI

tSU

TPOSI, TNEGI

tHD

tLP

tLL

tLH

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Maxim DS33R11 specifications Transmit-Side Timing, Elastic Store Enabled