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DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
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tF
t
R
TSYSCLK
TSERI
TCHCLK
t
t
SL
tSH
SP
TSSYNC
TCHBLK
tD3
tD3
t
t
tSU
HD
SU
tHD
NOTE 1: TSERI IS ONLY SAMPLED ON THE FALLING EDGE OF TSYSCLK WHEN THE TRANSMIT-SIDE ELASTIC STORE IS ENABLED.
NOTE 2: TCHCLK AND TCHBLK ARE SYNCHRONOUS WITH TSYSCLK WHEN THE TRANSMIT-SIDE ELASTIC STORE IS ENABLED.
TDCLKO
TPOSO, TNEGO
tDD
tF
t
R
TDCLKI
TPOSI, TNEGI
t
t
LL
tLH
LP
tHD
tSU