Maxim DS33R11 specifications Programmable In-Band Loop Code Generation and Detection

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver

10.19 Programmable In-Band Loop Code Generation and Detection

The transceiver has the ability to generate and detect a repeating bit pattern from one to eight bits or 16 bits in length. This function is available only in T1 mode. To transmit a pattern, the user loads the pattern into the transmit code-definition registers (TR.TCD1 and TR.TCD2) and selects the proper length of the pattern by setting the TC0 and TC1 bits in the in-band code control (TR.IBCC) register. When generating a 1-, 2-, 4-, 8-, or 16-bit pattern, both transmit code-definition registers must be filled with the proper code. Generation of a 3-, 5-, 6-, and 7- bit pattern only requires TR.TCD1 to be filled. Once this is accomplished, the pattern is transmitted as long as the TLOOP control bit (TR.T1CCR1.0) is enabled. Normally (unless the transmit formatter is programmed to not insert the F-bit position) the framer overwrites the repeating pattern once every 193 bits to send the F-bit position.

For example, to transmit the standard “loop-up” code for CSUs, which is a repeating pattern of ...10000100001... , set TR.TCD1 = 80h, TR.IBCC = 0, and TR.T1CCR1.0 = 1.

The framer has three programmable pattern detectors. Typically two of the detectors are used for “loop-up” and “loop-down” code detection. The user programs the codes to be detected in the receive up-code definition (TR.RUPCD1 and TR.RUPCD2) registers and the receive down-code definition (TR.RDNCD1 and TR.RDNCD2) registers, and the length of each pattern is selected through the TR.IBCC register. There is a third detector (spare) that is defined and controlled through the TR.RSCD1/ TR.RSCD2 and TR.RSCC registers. When detecting a 16-bit pattern, both receive code-definition registers are used together to form a 16-bit register. For 8-bit patterns, both receive code-definition registers are filled with the same value. Detection of a 1-, 2-, 3-, 4-, 5-, 6-, and 7-bit pattern only requires the first receive code-definition register to be filled. The framer detects repeating pattern codes in both framed and unframed circumstances with bit error rates as high as 10E-2. The detectors are capable of handling both F-bit inserted and F-bit overwrite patterns. Writing the least significant byte of the receive code- definition register resets the integration period for that detector. The code detector has a nominal integration period of 36ms. Hence, after about 36ms of receiving a valid code, the proper status bit (LUP at TR.SR3.5, LDN at TR.SR3.6, and LSPARE at TR.SR3.7) is set to a 1. Normally codes are sent for a period of five seconds. It is recommended that the software poll the framer every 50ms to 1000ms until five seconds has elapsed to ensure the code is continuously present.

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