DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver

Figure 6-4. Receive and Transmit T1/E1/J1 Framer

RPOS RNEG RCLK

TPOS TNEG TCLK

INTERNAL

SIGNALS

FROM

LIU

FRAMER LOOPBACK

 

 

REC

REC

 

 

 

HDLC #1

HDLC #2

 

 

 

128 Byte

128 Byte

 

 

 

FIFO

FIFO

 

 

DATA

MAPPER

MAPPER

DATA

RECEIVE

CLOCK

 

PAYLOAD

CLOCK

 

 

FRAMER

 

 

 

SYNC

 

LOOPBACK

SYNC

FRAMER

CLOCK

 

CLOCK

 

SYNC

 

 

SYNC

TRANSMIT

 

 

 

 

 

DATA

MAPPER

MAPPER

DATA

 

 

 

 

INTERNAL

 

 

XMIT

XMIT

SIGNALS

 

 

HDLC #1

HDLC #2

TO

 

 

128 Byte

128 Byte

BACKPLANE

 

 

FIFO

FIFO

INTERFACE

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Page 23
Image 23
Maxim DS33R11 specifications Data, Loopback Sync Framer