Maxim DS33R11 specifications Transmit Byte Sync Functional Timing, MII and Rmii Interfaces

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver

The DS33R11 provides the TBSYNC signal as a byte boundary indication to an external interface when X.86 (LAPS) functionality is selected. The functional timing of TBSYNC is shown in the following figure.TBSYNC is active high on the last bit of the byte being shifted out, and occurs every 8 bits. For the serial receiver interface, RBSYNC is used to provide byte boundary indication to the DS33R11 when X.86 (LAPS) mode is used. The functional timing is shown in Figure 12-3. In X.86 Mode, the receiver expects the RBSYNC byte indicator as shown in Figure 12-4.

Figure 12-3. Transmit Byte Sync Functional Timing

TCLKE

TBYSYNC

TSERO

last bit

1st bit

Figure 12-4. Receive Byte Sync Functional Timing

RCLKI

RBYSYNC

RSERI

last bit

1st bit

12.2 MII and RMII Interfaces

The MII Interface Transmit Port has its own TX_CLK and data interface. The data TXD [3:0] operates synchronously with TX_CLK. The LSB is presented first. TX_CLK should be 2.5MHz for 10Mbit/s operation and 25MHz for 100Mbit/s operation. TX_EN is valid at the same time as the first byte of the preamble. In DTE Mode TX_CLK is input from the external PHY. In DCE Mode, the DS33R11 provides TX_CLK, derived from an external reference (SYSCLKI).

Figure 12-5. MII Transmit Functional Timing

TX_CLK
TXD[3:0]
	P	R	E	A	E	M
TX_EN

B

L

E

F

C

S

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