T1/E1/J1, Ethernet MAC, Bert Refclk Arbiter

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver

Figure 9-1. Clocking for the DS33R11

MCLK

XTALD 8XCLK

BPCLK

TDCLKI TDCLKO

TSYSCLK

TCHBLK TCHCLK

TCLKT

TCLKE TDEN

μP Port

CLAD

RECEIVE ETHERNET TRANSMIT

CLAD

SYSCLKI

CIR CONTROLLER

RECEIVETRANSMIT LIULIU

TRANSMIT FRAMER

SERIAL

PORTPORT

PACKET HDLC/X.86

REF_CLKO

TTIP

MUX

RX_CLK

TRING

TRANSCEIVER

HDLC

ETHERNET MAC

T1/E1/J1

MAPPER

BERT

REF_CLK

BERT

ARBITER

HDLC

RTIP

MUX

RECEIVIE FRAMER

PACKET HDLC/X.86

TX_CLK

RRING

SERIAL

MDC

JTAG2

JTAG1

SDRAM PORT

JTCLK2

RDCLKI RDCLKO

RSYSCLK RCHBLK RCHCLK RCLKO

RCLKI

RDEN

SDCLK

JTCLK1

NOTE THAT THE CLOCKING OPTIONS OF THE INTEGRATED T1/E1/J1 TANSCEIVER ARE DISCUSSED IN SECTION 10.1.

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Maxim DS33R11 specifications T1/E1/J1, Ethernet MAC, Bert Refclk Arbiter

Contents

DS33R11 Part Temp Range PIN-PACKAGE Table of Contents Integrated T1/E1/J1 Transceiver Device Registers Operating Parameters List of Figures 308 List of Tables Description Page X.86 Link Access Protocol for SONET/SDH Ethernet Mapping GeneralMicroprocessor Interface Hdlc Ethernet Mapping MAC Interface Committed Information Rate CIR ControllerSdram Interface Jitter Attenuator T1/E1/J1 Line InterfaceClock Synthesizer 12 T1/E1/J1 Framer TDM Bus Test and Diagnostics Specifications Compliance T1-Related Telecommunications Specifications Ethernet-to-WAN Extension With or Without Framing B8ZS BOCCRC ESF Major Operating Modes Clad Ttip Transmit Framer MUX Tring BertRtip Rring MUX JTAG2 Transmit Serial Port Packet HDLC/X.86 CIR Controller Clock Jtag Host Interface Receive and Transmit T1/E1/J1 LIU Data Loopback Sync Framer Sync Rsync Rmsync Rfsync Internal Rdata Signals Rchclk From Sync Signaling Tseri TsigRlink Rlclk IOZ Pin Functional Description Detailed Pin DescriptionsName PIN Type Function Microprocessor Port Chip Select for Protocol Conversion Device This pin must be Read Data Strobe Intel Mode The DS33R11 drives the data busName PIN Type Function Receive Data 0 through 1 Rmii Two bits of received data Name PIN Type Function MII/RMII PHY PortReceive Data 0 through 3 MII Four bits of received data Reference Clock Rmii and MII When in Rmii mode, all signals Transmit Data 0 through 3MII TXD 30 is presentedTransmit Data 0 through 1RMII Two bits of data TXD Reference Clock Output Rmii and MII a derived clock output Sdcs Name PIN Type Function PHY Management BUSSdram Interface Sdram Data Bus Bits 0 to 31 The 32 pins of the Sdram data Name PIN Type Function T1/E1/J1 Analog Line Interface T1/E1/J1 Transmit Framer Interface Ethernet Mapper Transmit Serial Interface T1/E1/J1 Receive Framer Interface Receive Multiframe Sync for the T1/E1/J1 Transceiver An Receive System Clock for the Transceiver 1.544MHzReceive Frame Sync Pre Receive Elastic Store for T1/E1/J1 T1/E1/J1 FRAMER/LIU Interim Signals Transmit Negative-Data Output Updated on the rising edge Transmit Positive-Data Output Updated on the rising edgeTransmit Elastic Store Output Updated on the rising edge Transmit Clock Output from the T1/E1/J1 Framer Buffered Name PIN Type Function Hardware and Status Pins Mode Control for Processor InterfaceT1/E1/J1 Receive Signaling-Freeze Output Set high when Queue Overflow for Ethernet Mapper This pin goes high when Name PIN Type Function System Clocks Name PIN Type Function Jtag Interface Name PIN Type Function Power Supplies Receive Analog Positive Supply Connect to 3.3V power supplyReceive Analog Signal Ground Connect to the common supply Transmit Analog Signal Ground Connect to the common supply Ball BGA Pinout Functional Description Processor Interface Read-Write/Data Strobe ModesClear on Read Interrupt and Pin Modes Ethernet Mapper Clocks Clocking Options for the Ethernet InterfaceRmiimiis Speed DCE/ DTE Refclko Rxclk PIN Output Input Txclk Bert Refclk Arbiter T1/E1/J1Ethernet MAC Ethernet Interface Clock Modes Serial Interface Clock Modes Reset Function Location Comments Resets and Low Power ModesReset Functions Initialization and Configuration Global ResourcesPer-Port Resources Example Device Initialization Sequence Device Interrupts Drawing Legend Pin Interrupt Information Registers Status RegistersInformation Registers Serial Interface Connections and Queues Register Function Registers Related to Connections and QueuesArbiter Options for Flow Control Type ModeFlow Control Full Duplex Flow Control Half Duplex Flow Control Host-Managed Flow Control Ethernet Interface Port Ieee 802.3 Ethernet Frame Registers Related to Setting the Ethernet Port Register Name Function Configured as DTE Connected to an Ethernet PHY in MII Mode DTE and DCE Mode DS33R11 Configured as a DCE in MII Mode Ethernet MAC Address Register Description MAC Control RegistersMAC Status Registers MII Mode Options Rmii Mode PHY MII Management Block and Mdio Interface Bert FeaturesBert in the Ethernet Mapper Prbs Synchronization Receive Data InterfaceReceive Pattern Detection Pattern Generation Repetitive Pattern SynchronizationPattern Monitoring Transmit Packet Processor Error InsertionPerformance Monitoring Update Receive Packet Processor 11. Hdlc Encapsulation of MAC Frame 19 X.86 Encoding and Decoding 12. Laps Encoding of MAC Frames Concept 13. X.86 Encapsulation of the MAC frame Page Committed Information Rate Controller 10.1 T1/E1/J1 Clocks T1/E1/J1 Clock Map T1/E1/J1 Transmit Clock Source Per-Channel Operation10.3 T1/E1/J1 Transceiver Interrupts TCSS1 TCSS0 Transmit Clock Source AIS-CI and RAI-CI Generation and Detection 10.4 T1 Framer/Formatter Control and Status10.4.1 T1 Transmit Transparency 10.4.3 T1 Receive-Side Digital-Milliwatt Code Generation T1 Alarm CriteriaAlarm SET Criteria Clear Criteria 10.5 E1 Framer/Formatter Control and Status E1 Sync/Resync CriteriaFrame or Sync Criteria Resync Criteria Multiframe Level ITU Spec E1 Alarm Criteria Automatic Alarm GenerationAlarm SET Criteria Clear Criteria ITU Specification Per-Channel Loopback Error Counters T1 Line Code Violation Counting OptionsE1 Line-Code Violation Counting Options Line-Code Violation Counter TR.LCVCR Framing Mode T1 Path Code Violation Counting ArrangementsPath Code Violation Count Register TR.PCVCR Counted Bit Counter TR.EBCR T1 Frames Out-of-Sync Counting ArrangementsFrames Out-of-Sync Count Register TR.FOSCR 10.8 DS0 Monitoring Function Change-of-State Signaling OperationProcessor-Based Receive Signaling Hardware-Based Receive Signaling Receive Signaling Reinsertion at RseroForce Receive Signaling All Ones Receive Signaling Freeze Processor-Based Transmit Signaling 10.9.3.1 T1 Mode Hardware-Based Transmit Signaling 10.9.3.2 E1 ModeTime Slot Numbering Schemes Channel Phone Per-Channel Idle Code Generation 10. Idle-Code Array Address MappingBits 0 to 5 of Iaar Maps to Channel Idle-Code Programming Examples Example 10.12.1.1 T1 Mode 10.12.1.2 E1 ModeChannel Blocking Registers Elastic Stores Operation 11. Elastic Store Delay After Initialization Minimum Delay ModeInitialization Register BIT Delay Transmit Elastic Store 10.13 G.706 Intermediate CRC-4 Updating E1 Mode Only CRC-4 Recalculate Method 10.14 T1 Bit-Oriented Code BOC Controller Transmit BOCReceive BOC Transmit a BOC Method 2 Internal Register Scheme Based on CRC4 Multiframe Additional Sa and International Si Bit Operation E1 OnlyMethod 1 Internal Register Scheme Based on Double-Frame Hdlc Configuration Additional Hdlc Controllers in T1/E1/J1 Transceiver 12. Hdlc Controller Registers Register Channels Fifo ControlHdlc Mapping Receive Hdlc Code Example Fifo InformationReceive Packet-Bytes Available Receive Section Legacy FDL Support T1 ModeOverview 10.18 D4/SLC-96 Operation Transmit Section Programmable In-Band Loop Code Generation and Detection Receiver Line Interface Unit LIULIU Operation Receive Level Indicator and Threshold Interrupt Receive G.703 Synchronization Signal E1 ModeMonitor Mode T1/E1 Transmit BPV Error Insertion Transmit G.703 Synchronization Signal E1 ModeTransmitter Transmit Short-Circuit Detector/Limiter Clock Data CMI Mclk PrescalerCMI Code Mark Inversion Option 13. Transformer Specifications Specification Recommended ValueRecommended Circuits -7. Basic Interface DS33R11 E1 Transmit Pulse Template 10. Jitter Tolerance T1 Mode E1 Mode Xtald Mclk Bert StatusBert Mapping 15. Simplified Diagram of Bert in Network Direction Bert Error Counter Bert Repetitive Pattern SetBert Bit Counter Bert Alternating Word-Count Rate Payload Error-Insertion Function T1 Mode Only 14. Transmit Error-Insertion Setup Sequence15. Error Insertion Examples Number-of-Errors Registers Programmable Backplane Clock Synthesizer Fractional T1/E1 Support T1 Transmit 114 E1 Transmit E1 Transmit Flow Diagram 116 Register Address Map Mapper Chip Global Arbiter Bert Serial EthernetInterfac Port Select Registers Interface Transceiver Register Bit Maps Global Ethernet Mapper Register Bit MapGlobal Ethernet Mapper Register Bit Map Name Arbiter Register Bit Map Bert Register Bit MapArbiter Register Bit Map Bert Register Bit Map Serial Interface Register Bit Map Serial Interface Register Bit Map 114h Ethernet Interface Register Bit Map Ethernet Interface Register Bit Map MAC Indirect Register Bit Map MAC Register Bit Map 200h T1/E1/J1 Transceiver Register Bit Map Active when CST = 019 01A 035 050 06A 085 0AA 0AB0AC 0AD 0CA 0CB0CC 0CD 0DC 0DD0DE 0DF GL.IDRH Global Register Definitions for Ethernet MapperGL.IDRL GL.CR1 GL.BLR GL.LIE GL.RTCALGL.SRCALS GL.SIS GL.LISGL.SIE GL.BIE GL.TRQIEGL.TRQIS GL.BIS GL.CON1 GL.C1QPR GL.BISTEN GL.BISTPF GL.SDMODE1 GL.SDRFTC GL.SDMODE2GL.SDMODEWS Arbiter Registers Arbiter Register Bit DescriptionsAR.RQSC1 AR.TQSC1 Bert Registers BCRBert Control Register 80h Bpclr Bpchr BSPB0R BSPB1RBSPB2R BSPB3R Teicr BSR Bsrl Bsrie RBECB0R RBECB1RRBECR2 RBCB0 RBCB3 RBCB1RBCB2 Serial Interface Registers Serial Interface Transmit and Common RegistersLI.TSLCR LI.RSTPD LI.LPBK LI.TPPCL LI.TIFGC LI.TEPLC Transmit Errored Packet High Control Register Cleanup routineLI.TEPHC 0C7h LI.TPPSRIE LI.TPPSRLI.TPPSRL LI.TPCR2 LI.TPCR0LI.TPCR1 LI.TBCR0 LI.TBCR1LI.TBCR2 LI.TBCR3 LI.THPMUU LI.THPMUS 11.5.2 X.86 Registers LI.TX86EDELI.TRX86A LI.TRX8C LI.TRX86SAPIL LI.CIR LI.RPPCL Receive Serial InterfaceLI.RSLCR LI.RPPSR LI.RMPSCLLI.RMPSCH LI.RPPSRL Receive Packet Processor Status Register Latched105h Repl Rapl Ripdl Rspdl Rlpdl Repcl Rapcl Rspcl Receive Packet Processor Status Register Interrupt Enable LI.RPPSRIE106h Repie Rapie Ripdie Rspdie Rlpdie Repcie Rapcie Rspcie LI.RPCB2 LI.RPCB0LI.RPCB1 LI.RFPCB2 LI.RFPCB0LI.RFPCB1 LI.RAPCB2 LI.RAPCB0LI.RAPCB1 LI.RSPCB2 LI.RSPCB0LI.RSPCB1 LI.RBC0 LI.RBC1LI.RBC2 LI.RBC3 LI.RAC0 LI.RAC1LI.RAC2 LI.RAC3 LI.RX86S LI.RHPMUULI.RHPMUS LI.TQHT LI.RX86LSIELI.TQLT LI.TQTIE 126hLI.TQCTLS 127h Ethernet Interface Registers Ethernet Interface Register Bit DescriptionsSU.MACRADL SU.MACRADH SU.MACRD1 SU.MACRD2SU.MACRD3 SU.MACWD0 SU.MACWD1 SU.MACWD2SU.MACWD3 SU.MACAWL SU.MACAWH SU.MACRWC SU.LPBK SU.GCR SU.TFRC Transmit Frame Resend Control151h Ncfq Tprhbc Tprcb SU.TFSL SU.TFSH SU.RFSB2 SU.RFSB0SU.RFSB1 MCF SU.RFSB3157h SU.RMFSRL SU.RMFSRHSU.RQLT SU.RQHT SU.QRIE SU.QCRLS SU.RFRC Receive Frame Rejection Control15Eh Ucfr Cfrr Lerr Crcerr DBR Miier BFR MAC Registers SU.MACCR Bit Random Number Generator Bits Used SU.MACMIIA SU.MACMIID SU.MACFCR SU.MMCCTRL Reserved MAC Reserved Control Register010Ch indirect 010Dh 0110h indirect 0111h0112h 0113h SU.RxFrmCtr MAC All Frames Received Counter0200h indirect 0201h SU.RxFrmOkCtr MAC Frames Received OK Counter0204h indirect 0205h SU.TxFrmCtr MAC All Frames Transmitted Counter0300h indirect 0301h SU.TxBytesCtr MAC All Bytes Transmitted Counter0308h indirect 0309h SU.TxBytesOkCtr MAC Bytes Transmitted OK Counter030Ch indirect 030Dh SU.TxFrmUndr MAC Transmit Frame Under Run Counter0334h indirect 0335h SU.TxBdFrmCtr MAC All Frames Aborted Counter0338h indirect 0339h Master Mode Register Effect On Output Pins11.7 T1/E1/J1 Transceiver Registers TR.MSTRREG Configuration Register Bit 6 Rsync Mode Select 2 RSMS2TR.IOCR1 Bit 1 Tsync I/O Select Tsio 0 = Tsync is an input TR.IOCR2 TR.T1RCR1 OOF2 OOF1 Bit 6 Receive Frame Mode Select RFM 0 = D4 framing mode Bit 5 Receive B8ZS Enable RB8ZSBit 1 Receive Japanese CRC6 Enable RJC TR.T1RCR2 TR.T1TCR1 TB8ZS TSLC96 Tzse FBCT2 FBCT1 TD4YM TB7ZS Bit 7 Transmit B8ZS Enable TB8ZSTR.T1TCR2 Bit 2 Transmit Frame Mode Select TFM 0 = D4 framing mode TR.SSIE1 T1 ModeTR.T1CCR1 T1 Common Control Register TR.SSIE2 E1 Mode TR.SSIE1 E1 ModeSoftware Signaling Insertion Enable TR.SSIE4 TR.SSIE3 E1 ModeLcaw TR.T1RDMR3 TR.T1RDMR1TR.T1RDMR2 TR.IDR TR.INFO1 TR.INFO2 11hBits 0 3 Receive Level Bits RL0 to RL3. Real-time bits RL3 RL2 RL1 RL0 TR.IIR2 TR.INFO3TR.IIR1 Ilut Timer Rscos Jalt Lrcl Tcle Tocd Lolitc TR.SR1Status Register 16h TR.IMR1 Interrupt Mask Register17h Bit 7 Input Level Under Threshold Ilut 0 = interrupt masked Ryelc RUA1C Frclc Rlosc TR.SR218h Bit 0 Receive Loss-of-Sync Condition Rlos TR.IMR219h Lspare LDN LUP Lotc Lorc V52LNK Rdma RRA TR.SR31Ah TR.IMR3 TR.SR4 1ChRAIS-CI Rsao Rsaz TMF TAF RMF Rcmf RAF Bit 2 Receive Multiframe Event RMF TR.IMR4 1DhBit 7 Receive AIS-CI Event RAIS-CI Bit 3 Transmit Align Frame Event TAF 0 = interrupt masked Tesf Tesem Tslip Resf Resem Rslip TR.SR51Eh TR.IMR5 1Fh TR.SR6, TR.SR7 Hdlc #1 Status RegisterHdlc #2 Status Register 20h, 22h TR.IMR6, TR.IMR7 TR.INFO4 TR.INFO5, TR.INFO6PS2 PS1 PS0 TR.SR8 TR.IMR8 Bbed Bbco BEC0 BRA1 BRA0 Brlos Bsync TR.SR926h TR.IMR9 TR.PCPR Per-Channel Pointer Register28h Rsaoics Rsrcs Rfcs Brcs Thscs Peics Tfcs Btcs TR.PCDR1 TR.PCDR2TR.PCDR3 TR.PCDR4 TR.INFO7 TR.H1RC, TR.H2RCHdlc #1 Receive Control Hdlc #2 Receive Control 31h, 32h TR.E1RCR1 TR.E1RCR2 TR.E1TCR1 RBF1 RBF0 TR.E1TCR2TR.BOCC TR.RSCSE1, TR.RSCSE2, TR.RSCSE3, TR.RSCSE4 TR.RSINFO1, TR.RSINFO2, TR.RSINFO3, TR.RSINFO4MSB LSB Grsre RFE RFF Rccs Tccs Frsao Signaling Control RegisterTR.SIGCR Error-Counter Configuration Register Bit 5 Error-Counter Update Select EcusBit 4 Error-Accumulation Mode Select Eams Bit 2 Pcvcr Fs-Bit Error-Report Enable Fsbe TR.LCVCR1 TR.LCVCR2TR.PCVCR1 TR.PCVCR2 TR.FOSCR1 TR.FOSCR2TR.EBCR1 TR.EBCR2 TR.LBCR Loopback Control Register4Ah Liuc LLB RLB PLB FLB TR.PCLR1 TR.PCLR2TR.PCLR3 TR.PCLR4 TR.ESCR Elastic Store Control Register4Fh Tesalgn Tesr Tesmdm Tese Resalgn Resr Resmdm Rese 50h to 5Fh Transmit Signaling Registers E1 Mode, CAS FormatTR.TS1 to TR.TS16 Transmit Signaling Registers E1 Mode, CCS Format 50h to 5Bh Transmit Signaling Registers T1 Mode, ESF FormatTR.TS1 to TR.TS12 Transmit Signaling Registers T1 Mode, D4 Format CH2-A CH2-BCH1-A CH1-B CH4-A CH4-B Receive Signaling Registers T1 Mode, ESF Format Receive Signaling Registers T1 Mode, D4 FormatTR.RS1 to TR.RS12 60h to 6Bh Receive Signaling Registers E1 Mode, CAS Format Receive Signaling Registers E1 Mode, CCS FormatTR.RS1 to TR.RS16 60h to 6Fh TR.CCR1 TCSS1 TCSS0 TR.CCR3 TR.CCR2BPCS1 BPCS0 TR.TDS0SEL TR.CCR4RLT3 RLT2 RLT1 RLT0 TR.RDS0M TR.TDS0MTR.RDS0SEL TR.LIC1 Bit 6 Automatic Gain Control Enable Agce Network Mode GC5 GC4 GC3 GC2 GC1 GC0TR.TLBC T1, Impedance Match Off TR.LIC2 79hETS Lirst Ibpv TUA1 Jamux Scld Clds Bit 7 E1/T1 Select ETS TR.LIC3 MM1 MM0 TR.LIC4 MPS1 MPS0 JamuxMclk MPS1 MPS0 Jamux TT1 TT0 TR.IAAR Gric Gtic FunctionTR.PCICR TR.TCICE1 TR.TCICE2 TR.TCICE3TR.TCICE4 TR.RCICE1 TR.RCICE2 TR.RCICE3TR.RCICE4 TR.RCBR1 TR.RCBR4 TR.RCBR2TR.RCBR3 TR.TCBR1 TR.TCBR2TR.TCBR3 TR.TCBR4 TR.H1TC, TR.H2TC Hdlc #1 Transmit ControlHdlc #2 Transmit Control 90h, A0h RFHWM2 RFHWM1 RFHWM0 TR.H1FC, TR.H2FCTFLWM2 TFLWM1 TFLWM0 Register Name TR.H1RCS1, TR.H1RCS2, TR.H1RCS3, TR.H1RCS4 A2h, A3h, A4h, A5hBit 3 Receive Hdlc Channel Select Bit Bit 2 Receive Hdlc Channel Select Bit TR.H1RTSBS, TR.H2RTSBS Hdlc # 1 Receive Time Slot Bits/Sa Bits SelectHdlc # 2 Receive Time Slot Bits/Sa Bits Select 96h, A6h RCB8SE RCB7SE RCB6SE RCB5SE RCB4SE RCB3SE RCB2SE RCB1SE Register Name TR.H1TCS1, TR.H1TCS2, TR.H1TCS3, TR.H1TCS4 A7h, A8h, A9h, AAhBit 3 Transmit Hdlc Channel Select Bit Bit 2 Transmit Hdlc Channel Select Bit TR.H1TTSBS, TR.H2TTSBS TR.H1RPBA, TR.H2RPBA TR.H1TF, TR.H2TF TR.H1RF, TR.H2RF TR.H1TFBA, TR.H2TFBA TR.IBCCTC1 TC0 RUP2 RUP1 RUP0 TR.TCD1 TR.TCD2Transmit Code Definition Register B8h BAh TR.RUPCD2Receive Up-Code Definition Register TR.RDNCD1 Receive Down-Code Definition RegisterBBh TR.RDNCD2 TR.RSCC In-Band Receive Spare Control RegisterBDh RSC2 RSC1 RSC0 TR.RSCD1 TR.RSCD2 TR.RFDL TR.BOCC.4 = Receive FDL RegisterC0h RBOC5 RBOC4 RBOC3 RBOC2 RBOC1 RBOC0 TR.TFDL TR.RFDLM1, TR.RFDLM2 TR.RAF Receive Align Frame RegisterC6h TR.RNAF TR.RSiAF Received Si Bits of the Align FrameC8h TR.RSiNAF TR.RRA TR.RSa5 Received Sa5 BitsCCh TR.RSa6 TR.RSa7 Received Sa7 BitsCEh TR.RSa8 TR.TAF TR.TNAF TR.TSiAF Transmit Si Bits of the Align FrameD2h TR.TSiNAF TR.TRA TR.TSa5 Transmitted Sa5 BitsD6h TR.TSa6 TR.TSa7 Transmit Sa7 BitsD8h TR.TSa8 TR.TSACR TR.BAWC TR.BRP1 TR.BRP2TR.BRP3 TR.BRP4 TR.BC1 PS1 PS0 RPL3 RPL2 RPL1 RPL0 TR.BC2EIB2 EIB1 EIB0 TR.BBC1 TR.BBC2TR.BBC3 TR.BBC4 TR.BEC1 EC7 EC6 EC5 EC4 EC3 EC2 EC1 EC0TR.BEC2 EC9 EC8 TR.BIC TR.ERC ER3 ER2 ER1 ER0 Number-of-Errors TR.NOE1ECh TR.NOE2 TR.NOEL1 TR.NOEL2 Functional Serial I/O Timing Tx Serial Interface Functional Timing Transmit Byte Sync Functional Timing MII and Rmii Interfaces MII Transmit Half Duplex with a Collision Functional Timing FRAME# Rfsync RSYNC1 Rsync 2 RSYNC3 FRAME# RSYNC1 Rfsync RSYNC2 Rsync Rchclk Rchblk Rsync RfsyncRchclk RCHBLK1 Rsysclk Rser O Rchclk RCHBLK4 FRAME# TSYNC1 Tssync Tsync TSYNC3 Tchclk Tchblk Tchclk Tchblk 2,3 12.4 E1 Mode FRAME# Rfsync Rsync Rsysclk Rsero RSYNC2 Rmsync RSYNC3 Rchclk RchblkRmsync Rsync Rchclk RCHBLK3 TSYNC2 Rsync Tsync Rchclk Tchclk Rchblk TchblkFRAME# TSYNC1 Tssync 26. Transmit-Side Boundary Timing Elastic Store Disabled Tssync Tchclk Tchblk 312 Recommended DC Operating Conditions DC Electrical CharacteristicsParameter Symbol Conditions MIN TYP MAX Units Thermal Characteristics -3. Thermal Characteristics Theta-JA vs. AirflowParameter MIN TYP MAX AIR Flow THETA-JA Parameter Symbol MII Interface Transmit MII Interface10Mbps 100Mbps MIN TYP MAX Receive MII Interface Receive MII Interface Timing Rmii Interface Transmit Rmii Interface Transmit Rmii Interface Timing Receive Rmii Interface Receive Rmii Interface Timing MDC Mdio Parameter Symbol MIN TYP MAX UnitsMdio Interface Transmit WAN Interface 10. Transmit WAN Interface Tclke Tsero Tden Tbsync Receive WAN Interface 11. Receive WAN Interface Rclki Rseri Rden Rbsync Sdram Timing 12. Sdram Interface Timing 100 MHz Sdata RAS, ScasSWE, Sdcs SDA, SBA Parameter Symbol MIN TYP MAX Units Intel Bus Read Timing Modec = 11. Motorola Bus Read Timing Modec = RCHBLK, Rfsync RMSYNC, Rsync Rsero / Rdata / Rsig Rfsync / Rmsync Rchblk Rmsync Rsync Rsero / RsigSee Note 15. Receive Line Interface Timing 16. Receive Timing Delay Rclko to Bpclk Delay Rclko to Bpclk Parameter Symbol Conditions MIN TYP E1 MAX Units TSERI, TSIG, TDATA, TPOSI, Tnegi 17. Transmit-Side Timing 18. Transmit-Side Timing, Elastic Store Enabled 20. Jtag Interface Timing Diagram Jtag Interface Timing 17. Jtag Interface Timing Jtag Information Jtag TAP Controller State Machine Description Update-DR Update-IRSelect-IR-Scan Capture-IR TAP Controller State Diagram Instruction Register Instruction Codes for Ieee 1149.1 Architecture Instruction Selected Register Instruction Codes Jtag ID Codes ID Code Structure Test RegistersBoundary Scan Register Bypass Register Jtag Functional Timing Bypass Idcode State Package Information 15.1 256-Ball BGA 27mm x 27mm 56-G6004-001 Document Revision History Revision Description