DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver

Register Name:

SU.RxFrmCtr

 

 

 

 

 

 

Register Description:

MAC All Frames Received Counter

 

 

 

 

Register Address:

0200h (indirect)

 

 

 

 

 

 

0200h:

 

 

 

 

 

 

 

 

 

 

 

Bit #

31

30

29

 

 

28

27

26

25

24

 

Name

RXFRMC31

RXFRMC30

RXFRMC29

 

RXFRMC28

RXFRMC27

RXFRMC26

RXFRMC25

RXFRMC24

Default

0

0

0

 

 

0

0

0

0

0

 

0201h:

 

 

 

 

 

 

 

 

 

 

 

Bit #

23

22

21

 

 

20

19

18

17

16

 

Name

RXFRMC23

RXFRMC22

RXFRMC21

 

RXFRMC20

RXFRMC19

RXFRMC18

RXFRMC17

RXFRMC16

Default

0

0

0

 

 

0

0

0

0

0

 

0202h:

 

 

 

 

 

 

 

 

 

 

 

Bit #

15

14

13

 

 

12

11

10

09

08

 

Name

RXFRMC15

RXFRMC14

RXFRMC13

 

RXFRMC12

RXFRMC11

RXFRMC10

RXFRMC9

RXFRMC8

Default

0

0

0

 

 

0

0

0

0

0

 

0203h:

 

 

 

 

 

 

 

 

 

 

 

Bit #

07

06

05

 

 

04

03

02

01

00

 

Name

RXFRMC7

RXFRMC6

RXFRMC5

 

RXFRMC4

RXFRMC3

RXFRMC2

RXFRMC1

RXFRMC0

 

Default

0

0

0

 

 

0

0

0

0

0

 

Bits 0 - 31: All Frames Received Counter (RXFRMC[0:31]) 32 bit value indicating the number of frames received. Each time a frame is received, this counter is incremented by 1. This counter resets only upon device reset, does not saturate, and rolls-over to zero upon reaching the maximum value. The user should ensure that the measurement period is less than the minimum length of time required for the counter to increment 2^32-1 times at the maximum frame rate. The user should store the value from the beginning of the measurement period for later calculations, and take into account the possibility of a roll-over to occurring.

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Maxim DS33R11 specifications SU.RxFrmCtr, MAC All Frames Received Counter, 0200h indirect, 0201h, 0202h, 0203h