Maxim DS33R11 LIST OF TABLES

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
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LIST OF TABLES
Table 2-1. T1-Related Telecommunications Specifications...................................................................................... 16
Table 7-1. Detailed Pin Descriptions......................................................................................................................... 25
Table 9-1. Clocking Options for the Ethernet Interface............................................................................................. 43
Table 9-2. Reset Functions........................................................................................................................................46
Table 9-3. Registers Related to Connections and Queues....................................................................................... 52
Table 9-4. Options for Flow Control........................................................................................................................... 53
Table 9-5. Registers Related to Setting the Ethernet Port........................................................................................ 57
Table 9-6. MAC Control Registers............................................................................................................................. 60
Table 9-7. MAC Status Registers.............................................................................................................................. 60
Table 10-1. T1/E1/J1 Transmit Clock Source ...........................................................................................................73
Table 10-2. T1 Alarm Criteria.................................................................................................................................... 75
Table 10-3. E1 Sync/Resync Criteria ........................................................................................................................76
Table 10-4. E1 Alarm Criteria.................................................................................................................................... 77
Table 10-5 T1 Line Code Violation Counting Options............................................................................................... 78
Table 10-6. E1 Line-Code Violation Counting Options.............................................................................................. 78
Table 10-7. T1 Path Code Violation Counting Arrangements................................................................................... 79
Table 10-8. T1 Frames Out-of-Sync Counting Arrangements ..................................................................................80
Table 10-9. Time Slot Numbering Schemes..............................................................................................................85
Table 10-10. Idle-Code Array Address Mapping....................................................................................................... 86
Table 10-11. Elastic Store Delay After Initialization ..................................................................................................89
Table 10-12. HDLC Controller Registers................................................................................................................... 94
Table 10-13. Transformer Specifications.................................................................................................................104
Table 10-14. Transmit Error-Insertion Setup Sequence..........................................................................................111
Table 10-15. Error Insertion Examples.................................................................................................................... 111
Table 11-1. Register Address Map.......................................................................................................................... 117
Table 11-2. Global Ethernet Mapper Register Bit Map ...........................................................................................118
Table 11-3. Arbiter Register Bit Map....................................................................................................................... 119
Table 11-4. BERT Register Bit Map........................................................................................................................ 119
Table 11-5. Serial Interface Register Bit Map..........................................................................................................120
Table 11-6. Ethernet Interface Register Bit Map..................................................................................................... 122
Table 11-7. MAC Indirect Register Bit Map............................................................................................................. 123
Table 11-8. T1/E1/J1 Transceiver Register Bit Map (Active when CST = 0) ..........................................................125
Table 13-1. Recommended DC Operating Conditions............................................................................................ 313
Table 13-2. DC Electrical Characteristics................................................................................................................ 313
Table 13-3. Thermal Characteristics....................................................................................................................... 314
Table 13-4. Theta-JA vs. Airflow .............................................................................................................................314
Table 13-5. Transmit MII Interface ..........................................................................................................................315
Table 13-6. Receive MII Interface ...........................................................................................................................316
Table 13-7. Transmit RMII Interface........................................................................................................................ 317
Table 13-8. Receive RMII Interface......................................................................................................................... 318
Table 13-9. MDIO Interface..................................................................................................................................... 319
Table 13-10. Transmit WAN Interface..................................................................................................................... 320
Table 13-11. Receive WAN Interface...................................................................................................................... 321
Table 13-12. SDRAM Interface Timing.................................................................................................................... 322
Table 13-13. AC Characteristics—Microprocessor Bus Timing.............................................................................. 324
Table 13-14. AC Characteristics: Receive Side...................................................................................................... 327
Table 13-15. AC Characteristics: Backplane Clock Synthesis................................................................................ 331
Table 13-16. AC Characteristics: Transmit Side..................................................................................................... 332
Table 13-17. JTAG Interface Timing .......................................................................................................................335
Table 14-1. Instruction Codes for IEEE 1149.1 Architecture ..................................................................................340
Table 14-2. ID Code Structure................................................................................................................................. 341