Maxim DS33R11 specifications Tsysclk, Tchclk Tchblk 2,3

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver

Figure 12-18. Transmit-Side 1.544MHz Boundary Timing (Elastic Store Enabled)

TSYSCLK

	CHANNEL 23	CHANNEL 24	CHANNEL 1
TSERI	LSB MSB	LSB	F MSB
TSSYNC
	CHANNEL 23	CHANNEL 24	CHANNEL 1
TSIG	A B C/A D/B	A B C/A D/B	A
TCHCLK

TCHBLK 1

NOTE 1: TCHBLK IS PROGRAMMED TO BLOCK CHANNEL 24 (IF THE TPCSI BIT IS SET, THEN THE SIGNALING DATA AT TSIG IS IGNORED DURING CHANNEL 24).

Figure 12-19. Transmit-Side 2.048MHz Boundary Timing (Elastic Store Enabled)

TSYSCLK

	CHANNEL 31	CHANNEL 32	CHANNEL 1
TSERI 1	LSB MSB	LSB	F4
TSSYNC
	CHANNEL 31	CHANNEL 32	CHANNEL 1
TSIG	A B C/A D/B	A B C/A D/B	A

TCHCLK

TCHBLK 2,3

NOTE 1: TSERI DATA IN CHANNELS 1, 5, 9, 13, 17, 21, 25, AND 29 IS IGNORED.

NOTE 2: TCHBLK IS PROGRAMMED TO BLOCK CHANNEL 31 (IF THE TPCSI BIT IS SET, THEN THE SIGNALING DATA AT TSIG WILL BE IGNORED).

NOTE 3: TCHBLK IS FORCED TO 1 IN THE SAME CHANNELS AS TSERI IS IGNORED (SEE NOTE 1).

NOTE 4: THE F-BIT POSITION FOR THE T1 FRAME IS SAMPLED AND PASSED THROUGH THE TRANSMIT-SIDE ELASTIC STORE INTO THE MSB BIT POSITION OF CHANNEL 1. (NORMALLY, THE TRANSMIT-SIDE FORMATTER OVERWRITES THE F-BIT POSITION UNLESS THE FORMATTER IS PROGRAMMED TO PASS THROUGH THE F-BIT POSITION.)

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