DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
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12.4 E1 MODE....................................................................................................................................308
13 OPERATING PARAMETERS ........................................................................................................313
13.1 THERMAL CHARACTERISTICS....................................................................................................... 314
13.2 MII INTERFACE............................................................................................................................315
13.3 RMII INTERFACE......................................................................................................................... 317
13.4 MDIO INTERFACE....................................................................................................................... 319
13.5 TRANSMIT WAN INTERFACE........................................................................................................ 320
13.6 RECEIVE WAN INTERFACE.......................................................................................................... 321
13.7 SDRAM TIMING..........................................................................................................................322
13.8 MICROPROCESSOR BUS AC CHARACTERISTICS........................................................................... 324
13.9 AC CHARACTERISTICS: RECEIVE-SIDE ........................................................................................327
13.10 AC CHARACTERISTICS: BACKPLANE CLOCK TIMING.....................................................................331
13.11 AC CHARACTERISTICS: TRANSMIT SIDE.......................................................................................332
13.12 JTAG INTERFACE TIMING............................................................................................................335
14 JTAG INFORMATION.................................................................................................................... 336
14.1 JTAG TAP CONTROLLER STATE MACHINE DESCRIPTION.............................................................337
14.2 INSTRUCTION REGISTER.............................................................................................................. 339
14.3 JTAG ID CODES.........................................................................................................................341
14.4 TEST REGISTERS........................................................................................................................ 341
14.4.1 Boundary Scan Register.....................................................................................................................341
14.4.2 Bypass Register..................................................................................................................................341
14.4.3 Identification Register .........................................................................................................................341
14.5 JTAG FUNCTIONAL TIMING .........................................................................................................342
15 PACKAGE INFORMATION............................................................................................................343
15.1 PACKAGE OUTLINE DRAWING OF 256-BGA (VIEW FROM BOTTOM OF DEVICE)..............................343
16 DOCUMENT REVISION HISTORY................................................................................................ 344