Maxim DS33R11 Jtag Interface Timing 17. Jtag Interface Timing, Jtag Interface Timing Diagram

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver

13.12 JTAG Interface Timing

Table 13-17. JTAG Interface Timing

(VDD3.3 = 3.3V ±5%,VDD1.8 = 1.8V ±5%, Tj = -40°C to +85°C.) (Note 1, Figure 13-20)

PARAMETER	SYMBOL	MIN	TYP	MAX	UNITS
JTCLK Clock Period	t1		1000		ns
JTCLK Clock High:Low Time (Note 2)	t2 : t3	50	500		ns
JTCLK to JTDI, JTMS Setup Time	t4	2			ns
JTCLK to JTDI, JTMS Hold Time	t5	2			ns
JTCLK to JTDO Delay	t6	2		50	ns
JTCLK to JTDO HIZ Delay	t7	2		50	ns
JTRST Width Low Time	t8	100			ns

Note 1: Timing parameters in this table are guaranteed by design (GBD).

Note 2: Clock can be stopped high or low

Figure 13-20. JTAG Interface Timing Diagram

JTCLK

JTDI, JTMS

t6

JTD0

JTRST

t1

t2 t3

t4 t5

t7

t8

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