Rsero / Rdata / Rsig, Rfsync / Rmsync | Maxim DS33R11 specs

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver

Figure 13-13. Receive-Side Timing

RCLKO
tD1
RSERO / RDATA / RSIG	1ST FRAME BIT

tD2

RSYNC 1

tD2

RFSYNC / RMSYNC

tD2

RCHCLK

tD2

RCHBLK

NOTE 1: RSYNC IS IN THE OUTPUT MODE.

NOTE 2: NO RELATIONSHIP BETWEEN RCHCLK AND RCHBLK AND OTHER SIGNALS IS IMPLIED.

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Image 328

Maxim DS33R11 specifications Rsero / Rdata / Rsig, Rfsync / Rmsync

Contents

DS33R11 Part Temp Range PIN-PACKAGE Table of Contents Integrated T1/E1/J1 Transceiver Device Registers Operating Parameters List of Figures 308 List of Tables Description Page X.86 Link Access Protocol for SONET/SDH Ethernet Mapping GeneralMicroprocessor Interface Hdlc Ethernet Mapping Sdram Interface Committed Information Rate CIR ControllerMAC Interface Clock Synthesizer T1/E1/J1 Line InterfaceJitter Attenuator 12 T1/E1/J1 Framer TDM Bus Test and Diagnostics Specifications Compliance T1-Related Telecommunications Specifications Ethernet-to-WAN Extension With or Without Framing B8ZS BOCCRC ESF Major Operating Modes Clad Ttip Transmit Framer MUX Tring BertRtip Rring MUX JTAG2 Transmit Serial Port Packet HDLC/X.86 CIR Controller Clock Jtag Host Interface Receive and Transmit T1/E1/J1 LIU Data Loopback Sync Framer Sync Rsync Rmsync Rfsync Internal Rdata Signals Rchclk From Sync Signaling Tseri TsigRlink Rlclk Name PIN Type Function Microprocessor Port Pin Functional Description Detailed Pin DescriptionsIOZ Name PIN Type Function Read Data Strobe Intel Mode The DS33R11 drives the data busChip Select for Protocol Conversion Device This pin must be Receive Data 0 through 3 MII Four bits of received data Name PIN Type Function MII/RMII PHY PortReceive Data 0 through 1 Rmii Two bits of received data Reference Clock Rmii and MII When in Rmii mode, all signals Transmit Data 0 through 3MII TXD 30 is presentedTransmit Data 0 through 1RMII Two bits of data TXD Reference Clock Output Rmii and MII a derived clock output Sdram Interface Name PIN Type Function PHY Management BUSSdcs Sdram Data Bus Bits 0 to 31 The 32 pins of the Sdram data Name PIN Type Function T1/E1/J1 Analog Line Interface T1/E1/J1 Transmit Framer Interface Ethernet Mapper Transmit Serial Interface T1/E1/J1 Receive Framer Interface Receive Frame Sync Pre Receive Elastic Store for T1/E1/J1 Receive System Clock for the Transceiver 1.544MHzReceive Multiframe Sync for the T1/E1/J1 Transceiver An T1/E1/J1 FRAMER/LIU Interim Signals Transmit Negative-Data Output Updated on the rising edge Transmit Positive-Data Output Updated on the rising edgeTransmit Elastic Store Output Updated on the rising edge Transmit Clock Output from the T1/E1/J1 Framer Buffered Name PIN Type Function Hardware and Status Pins Mode Control for Processor InterfaceT1/E1/J1 Receive Signaling-Freeze Output Set high when Queue Overflow for Ethernet Mapper This pin goes high when Name PIN Type Function System Clocks Name PIN Type Function Jtag Interface Name PIN Type Function Power Supplies Receive Analog Positive Supply Connect to 3.3V power supplyReceive Analog Signal Ground Connect to the common supply Transmit Analog Signal Ground Connect to the common supply Ball BGA Pinout Functional Description Processor Interface Read-Write/Data Strobe ModesClear on Read Interrupt and Pin Modes Ethernet Mapper Clocks Clocking Options for the Ethernet InterfaceRmiimiis Speed DCE/ DTE Refclko Rxclk PIN Output Input Txclk Ethernet MAC T1/E1/J1Bert Refclk Arbiter Ethernet Interface Clock Modes Serial Interface Clock Modes Reset Functions Resets and Low Power ModesReset Function Location Comments Initialization and Configuration Global ResourcesPer-Port Resources Example Device Initialization Sequence Device Interrupts Drawing Legend Pin Interrupt Information Registers Status RegistersInformation Registers Serial Interface Connections and Queues Arbiter Registers Related to Connections and QueuesRegister Function Flow Control Type ModeOptions for Flow Control Full Duplex Flow Control Half Duplex Flow Control Host-Managed Flow Control Ethernet Interface Port Ieee 802.3 Ethernet Frame Registers Related to Setting the Ethernet Port Register Name Function Configured as DTE Connected to an Ethernet PHY in MII Mode DTE and DCE Mode DS33R11 Configured as a DCE in MII Mode Ethernet MAC MAC Status Registers MAC Control RegistersAddress Register Description MII Mode Options Rmii Mode Bert in the Ethernet Mapper Bert FeaturesPHY MII Management Block and Mdio Interface Receive Pattern Detection Receive Data InterfacePrbs Synchronization Pattern Monitoring Repetitive Pattern SynchronizationPattern Generation Performance Monitoring Update Error InsertionTransmit Packet Processor Receive Packet Processor 11. Hdlc Encapsulation of MAC Frame 19 X.86 Encoding and Decoding 12. Laps Encoding of MAC Frames Concept 13. X.86 Encapsulation of the MAC frame Page Committed Information Rate Controller 10.1 T1/E1/J1 Clocks T1/E1/J1 Clock Map T1/E1/J1 Transmit Clock Source Per-Channel Operation10.3 T1/E1/J1 Transceiver Interrupts TCSS1 TCSS0 Transmit Clock Source 10.4.1 T1 Transmit Transparency 10.4 T1 Framer/Formatter Control and StatusAIS-CI and RAI-CI Generation and Detection Alarm SET Criteria Clear Criteria T1 Alarm Criteria10.4.3 T1 Receive-Side Digital-Milliwatt Code Generation 10.5 E1 Framer/Formatter Control and Status E1 Sync/Resync CriteriaFrame or Sync Criteria Resync Criteria Multiframe Level ITU Spec E1 Alarm Criteria Automatic Alarm GenerationAlarm SET Criteria Clear Criteria ITU Specification Per-Channel Loopback Error Counters T1 Line Code Violation Counting OptionsE1 Line-Code Violation Counting Options Line-Code Violation Counter TR.LCVCR Framing Mode T1 Path Code Violation Counting ArrangementsPath Code Violation Count Register TR.PCVCR Counted Frames Out-of-Sync Count Register TR.FOSCR T1 Frames Out-of-Sync Counting ArrangementsBit Counter TR.EBCR 10.8 DS0 Monitoring Function Processor-Based Receive Signaling Signaling OperationChange-of-State Hardware-Based Receive Signaling Receive Signaling Reinsertion at RseroForce Receive Signaling All Ones Receive Signaling Freeze Processor-Based Transmit Signaling 10.9.3.1 T1 Mode Hardware-Based Transmit Signaling 10.9.3.2 E1 ModeTime Slot Numbering Schemes Channel Phone Per-Channel Idle Code Generation 10. Idle-Code Array Address MappingBits 0 to 5 of Iaar Maps to Channel Idle-Code Programming Examples Example 10.12.1.1 T1 Mode 10.12.1.2 E1 ModeChannel Blocking Registers Elastic Stores Operation 11. Elastic Store Delay After Initialization Minimum Delay ModeInitialization Register BIT Delay Transmit Elastic Store 10.13 G.706 Intermediate CRC-4 Updating E1 Mode Only CRC-4 Recalculate Method 10.14 T1 Bit-Oriented Code BOC Controller Transmit BOCReceive BOC Transmit a BOC Method 1 Internal Register Scheme Based on Double-Frame Additional Sa and International Si Bit Operation E1 OnlyMethod 2 Internal Register Scheme Based on CRC4 Multiframe Hdlc Configuration Additional Hdlc Controllers in T1/E1/J1 Transceiver 12. Hdlc Controller Registers Hdlc Mapping Fifo ControlRegister Channels Receive Packet-Bytes Available Fifo InformationReceive Hdlc Code Example Overview Legacy FDL Support T1 ModeReceive Section 10.18 D4/SLC-96 Operation Transmit Section Programmable In-Band Loop Code Generation and Detection LIU Operation Line Interface Unit LIUReceiver Receive Level Indicator and Threshold Interrupt Receive G.703 Synchronization Signal E1 ModeMonitor Mode T1/E1 Transmit BPV Error Insertion Transmit G.703 Synchronization Signal E1 ModeTransmitter Transmit Short-Circuit Detector/Limiter CMI Code Mark Inversion Option Mclk PrescalerClock Data CMI 13. Transformer Specifications Specification Recommended ValueRecommended Circuits -7. Basic Interface DS33R11 E1 Transmit Pulse Template 10. Jitter Tolerance T1 Mode E1 Mode Bert Mapping Bert StatusXtald Mclk 15. Simplified Diagram of Bert in Network Direction Bert Error Counter Bert Repetitive Pattern SetBert Bit Counter Bert Alternating Word-Count Rate Payload Error-Insertion Function T1 Mode Only 14. Transmit Error-Insertion Setup Sequence15. Error Insertion Examples Number-of-Errors Registers Programmable Backplane Clock Synthesizer Fractional T1/E1 Support T1 Transmit 114 E1 Transmit E1 Transmit Flow Diagram 116 Register Address Map Mapper Chip Global Arbiter Bert Serial EthernetInterfac Port Select Registers Interface Transceiver Register Bit Maps Global Ethernet Mapper Register Bit MapGlobal Ethernet Mapper Register Bit Map Name Arbiter Register Bit Map Bert Register Bit MapArbiter Register Bit Map Bert Register Bit Map Serial Interface Register Bit Map Serial Interface Register Bit Map 114h Ethernet Interface Register Bit Map Ethernet Interface Register Bit Map MAC Indirect Register Bit Map MAC Register Bit Map 200h T1/E1/J1 Transceiver Register Bit Map Active when CST = 019 01A 035 050 06A 085 0AA 0AB0AC 0AD 0CA 0CB0CC 0CD 0DC 0DD0DE 0DF GL.IDRL Global Register Definitions for Ethernet MapperGL.IDRH GL.CR1 GL.BLR GL.SRCALS GL.RTCALGL.LIE GL.SIE GL.LISGL.SIS GL.TRQIS GL.TRQIEGL.BIE GL.BIS GL.CON1 GL.C1QPR GL.BISTEN GL.BISTPF GL.SDMODE1 GL.SDMODEWS GL.SDMODE2GL.SDRFTC Arbiter Registers Arbiter Register Bit DescriptionsAR.RQSC1 AR.TQSC1 Bert Registers BCRBert Control Register 80h Bpclr Bpchr BSPB0R BSPB1RBSPB2R BSPB3R Teicr BSR Bsrl Bsrie RBECB0R RBECB1RRBECR2 RBCB0 RBCB2 RBCB1RBCB3 Serial Interface Registers Serial Interface Transmit and Common RegistersLI.TSLCR LI.RSTPD LI.LPBK LI.TPPCL LI.TIFGC LI.TEPLC Transmit Errored Packet High Control Register Cleanup routineLI.TEPHC 0C7h LI.TPPSRL LI.TPPSRLI.TPPSRIE LI.TPCR1 LI.TPCR0LI.TPCR2 LI.TBCR0 LI.TBCR1LI.TBCR2 LI.TBCR3 LI.THPMUU LI.THPMUS 11.5.2 X.86 Registers LI.TX86EDELI.TRX86A LI.TRX8C LI.TRX86SAPIL LI.CIR LI.RSLCR Receive Serial InterfaceLI.RPPCL LI.RMPSCH LI.RMPSCLLI.RPPSR LI.RPPSRL Receive Packet Processor Status Register Latched105h Repl Rapl Ripdl Rspdl Rlpdl Repcl Rapcl Rspcl Receive Packet Processor Status Register Interrupt Enable LI.RPPSRIE106h Repie Rapie Ripdie Rspdie Rlpdie Repcie Rapcie Rspcie LI.RPCB1 LI.RPCB0LI.RPCB2 LI.RFPCB1 LI.RFPCB0LI.RFPCB2 LI.RAPCB1 LI.RAPCB0LI.RAPCB2 LI.RSPCB1 LI.RSPCB0LI.RSPCB2 LI.RBC0 LI.RBC1LI.RBC2 LI.RBC3 LI.RAC0 LI.RAC1LI.RAC2 LI.RAC3 LI.RHPMUS LI.RHPMUULI.RX86S LI.TQLT LI.RX86LSIELI.TQHT LI.TQTIE 126hLI.TQCTLS 127h Ethernet Interface Registers Ethernet Interface Register Bit DescriptionsSU.MACRADL SU.MACRADH SU.MACRD1 SU.MACRD2SU.MACRD3 SU.MACWD0 SU.MACWD1 SU.MACWD2SU.MACWD3 SU.MACAWL SU.MACAWH SU.MACRWC SU.LPBK SU.GCR SU.TFRC Transmit Frame Resend Control151h Ncfq Tprhbc Tprcb SU.TFSL SU.TFSH SU.RFSB1 SU.RFSB0SU.RFSB2 157h SU.RFSB3MCF SU.RMFSRL SU.RMFSRHSU.RQLT SU.RQHT SU.QRIE SU.QCRLS SU.RFRC Receive Frame Rejection Control15Eh Ucfr Cfrr Lerr Crcerr DBR Miier BFR MAC Registers SU.MACCR Bit Random Number Generator Bits Used SU.MACMIIA SU.MACMIID SU.MACFCR SU.MMCCTRL Reserved MAC Reserved Control Register010Ch indirect 010Dh 0110h indirect 0111h0112h 0113h SU.RxFrmCtr MAC All Frames Received Counter0200h indirect 0201h SU.RxFrmOkCtr MAC Frames Received OK Counter0204h indirect 0205h SU.TxFrmCtr MAC All Frames Transmitted Counter0300h indirect 0301h SU.TxBytesCtr MAC All Bytes Transmitted Counter0308h indirect 0309h SU.TxBytesOkCtr MAC Bytes Transmitted OK Counter030Ch indirect 030Dh SU.TxFrmUndr MAC Transmit Frame Under Run Counter0334h indirect 0335h SU.TxBdFrmCtr MAC All Frames Aborted Counter0338h indirect 0339h Master Mode Register Effect On Output Pins11.7 T1/E1/J1 Transceiver Registers TR.MSTRREG Configuration Register Bit 6 Rsync Mode Select 2 RSMS2TR.IOCR1 Bit 1 Tsync I/O Select Tsio 0 = Tsync is an input TR.IOCR2 TR.T1RCR1 OOF2 OOF1 Bit 6 Receive Frame Mode Select RFM 0 = D4 framing mode Bit 5 Receive B8ZS Enable RB8ZSBit 1 Receive Japanese CRC6 Enable RJC TR.T1RCR2 TR.T1TCR1 TR.T1TCR2 Bit 7 Transmit B8ZS Enable TB8ZSTB8ZS TSLC96 Tzse FBCT2 FBCT1 TD4YM TB7ZS Bit 2 Transmit Frame Mode Select TFM 0 = D4 framing mode TR.SSIE1 T1 ModeTR.T1CCR1 T1 Common Control Register Software Signaling Insertion Enable TR.SSIE1 E1 ModeTR.SSIE2 E1 Mode Lcaw TR.SSIE3 E1 ModeTR.SSIE4 TR.T1RDMR2 TR.T1RDMR1TR.T1RDMR3 TR.IDR TR.INFO1 TR.INFO2 11hBits 0 3 Receive Level Bits RL0 to RL3. Real-time bits RL3 RL2 RL1 RL0 TR.IIR1 TR.INFO3TR.IIR2 Ilut Timer Rscos Jalt Lrcl Tcle Tocd Lolitc TR.SR1Status Register 16h TR.IMR1 Interrupt Mask Register17h Bit 7 Input Level Under Threshold Ilut 0 = interrupt masked 18h TR.SR2Ryelc RUA1C Frclc Rlosc 19h TR.IMR2Bit 0 Receive Loss-of-Sync Condition Rlos 1Ah TR.SR3Lspare LDN LUP Lotc Lorc V52LNK Rdma RRA TR.IMR3 TR.SR4 1ChRAIS-CI Rsao Rsaz TMF TAF RMF Rcmf RAF Bit 2 Receive Multiframe Event RMF TR.IMR4 1DhBit 7 Receive AIS-CI Event RAIS-CI Bit 3 Transmit Align Frame Event TAF 0 = interrupt masked 1Eh TR.SR5Tesf Tesem Tslip Resf Resem Rslip TR.IMR5 1Fh TR.SR6, TR.SR7 Hdlc #1 Status RegisterHdlc #2 Status Register 20h, 22h TR.IMR6, TR.IMR7 PS2 PS1 PS0 TR.INFO5, TR.INFO6TR.INFO4 TR.SR8 TR.IMR8 26h TR.SR9Bbed Bbco BEC0 BRA1 BRA0 Brlos Bsync TR.IMR9 TR.PCPR Per-Channel Pointer Register28h Rsaoics Rsrcs Rfcs Brcs Thscs Peics Tfcs Btcs TR.PCDR1 TR.PCDR2TR.PCDR3 TR.PCDR4 TR.INFO7 TR.H1RC, TR.H2RCHdlc #1 Receive Control Hdlc #2 Receive Control 31h, 32h TR.E1RCR1 TR.E1RCR2 TR.E1TCR1 TR.BOCC TR.E1TCR2RBF1 RBF0 MSB LSB TR.RSINFO1, TR.RSINFO2, TR.RSINFO3, TR.RSINFO4TR.RSCSE1, TR.RSCSE2, TR.RSCSE3, TR.RSCSE4 TR.SIGCR Signaling Control RegisterGrsre RFE RFF Rccs Tccs Frsao Error-Counter Configuration Register Bit 5 Error-Counter Update Select EcusBit 4 Error-Accumulation Mode Select Eams Bit 2 Pcvcr Fs-Bit Error-Report Enable Fsbe TR.LCVCR1 TR.LCVCR2TR.PCVCR1 TR.PCVCR2 TR.FOSCR1 TR.FOSCR2TR.EBCR1 TR.EBCR2 TR.LBCR Loopback Control Register4Ah Liuc LLB RLB PLB FLB TR.PCLR1 TR.PCLR2TR.PCLR3 TR.PCLR4 TR.ESCR Elastic Store Control Register4Fh Tesalgn Tesr Tesmdm Tese Resalgn Resr Resmdm Rese TR.TS1 to TR.TS16 Transmit Signaling Registers E1 Mode, CAS Format50h to 5Fh Transmit Signaling Registers E1 Mode, CCS Format TR.TS1 to TR.TS12 Transmit Signaling Registers T1 Mode, ESF Format50h to 5Bh Transmit Signaling Registers T1 Mode, D4 Format CH2-A CH2-BCH1-A CH1-B CH4-A CH4-B Receive Signaling Registers T1 Mode, ESF Format Receive Signaling Registers T1 Mode, D4 FormatTR.RS1 to TR.RS12 60h to 6Bh Receive Signaling Registers E1 Mode, CAS Format Receive Signaling Registers E1 Mode, CCS FormatTR.RS1 to TR.RS16 60h to 6Fh TR.CCR1 TCSS1 TCSS0 BPCS1 BPCS0 TR.CCR2TR.CCR3 RLT3 RLT2 RLT1 RLT0 TR.CCR4TR.TDS0SEL TR.RDS0SEL TR.TDS0MTR.RDS0M TR.LIC1 Bit 6 Automatic Gain Control Enable Agce Network Mode GC5 GC4 GC3 GC2 GC1 GC0TR.TLBC T1, Impedance Match Off TR.LIC2 79hETS Lirst Ibpv TUA1 Jamux Scld Clds Bit 7 E1/T1 Select ETS TR.LIC3 MM1 MM0 TR.LIC4 MPS1 MPS0 JamuxMclk MPS1 MPS0 Jamux TT1 TT0 TR.IAAR Gric Gtic FunctionTR.PCICR TR.TCICE1 TR.TCICE2 TR.TCICE3TR.TCICE4 TR.RCICE1 TR.RCICE2 TR.RCICE3TR.RCICE4 TR.RCBR1 TR.RCBR3 TR.RCBR2TR.RCBR4 TR.TCBR1 TR.TCBR2TR.TCBR3 TR.TCBR4 TR.H1TC, TR.H2TC Hdlc #1 Transmit ControlHdlc #2 Transmit Control 90h, A0h TFLWM2 TFLWM1 TFLWM0 TR.H1FC, TR.H2FCRFHWM2 RFHWM1 RFHWM0 Register Name TR.H1RCS1, TR.H1RCS2, TR.H1RCS3, TR.H1RCS4 A2h, A3h, A4h, A5hBit 3 Receive Hdlc Channel Select Bit Bit 2 Receive Hdlc Channel Select Bit TR.H1RTSBS, TR.H2RTSBS Hdlc # 1 Receive Time Slot Bits/Sa Bits SelectHdlc # 2 Receive Time Slot Bits/Sa Bits Select 96h, A6h RCB8SE RCB7SE RCB6SE RCB5SE RCB4SE RCB3SE RCB2SE RCB1SE Register Name TR.H1TCS1, TR.H1TCS2, TR.H1TCS3, TR.H1TCS4 A7h, A8h, A9h, AAhBit 3 Transmit Hdlc Channel Select Bit Bit 2 Transmit Hdlc Channel Select Bit TR.H1TTSBS, TR.H2TTSBS TR.H1RPBA, TR.H2RPBA TR.H1TF, TR.H2TF TR.H1RF, TR.H2RF TR.H1TFBA, TR.H2TFBA TR.IBCCTC1 TC0 RUP2 RUP1 RUP0 TR.TCD1 TR.TCD2Transmit Code Definition Register B8h Receive Up-Code Definition Register TR.RUPCD2BAh TR.RDNCD1 Receive Down-Code Definition RegisterBBh TR.RDNCD2 TR.RSCC In-Band Receive Spare Control RegisterBDh RSC2 RSC1 RSC0 TR.RSCD1 TR.RSCD2 TR.RFDL TR.BOCC.4 = Receive FDL RegisterC0h RBOC5 RBOC4 RBOC3 RBOC2 RBOC1 RBOC0 TR.TFDL TR.RFDLM1, TR.RFDLM2 TR.RAF Receive Align Frame RegisterC6h TR.RNAF TR.RSiAF Received Si Bits of the Align FrameC8h TR.RSiNAF TR.RRA TR.RSa5 Received Sa5 BitsCCh TR.RSa6 TR.RSa7 Received Sa7 BitsCEh TR.RSa8 TR.TAF TR.TNAF TR.TSiAF Transmit Si Bits of the Align FrameD2h TR.TSiNAF TR.TRA TR.TSa5 Transmitted Sa5 BitsD6h TR.TSa6 TR.TSa7 Transmit Sa7 BitsD8h TR.TSa8 TR.TSACR TR.BAWC TR.BRP1 TR.BRP2TR.BRP3 TR.BRP4 TR.BC1 PS1 PS0 EIB2 EIB1 EIB0 TR.BC2RPL3 RPL2 RPL1 RPL0 TR.BBC1 TR.BBC2TR.BBC3 TR.BBC4 TR.BEC1 EC7 EC6 EC5 EC4 EC3 EC2 EC1 EC0TR.BEC2 EC9 EC8 TR.BIC TR.ERC ER3 ER2 ER1 ER0 Number-of-Errors TR.NOE1ECh TR.NOE2 TR.NOEL1 TR.NOEL2 Functional Serial I/O Timing Tx Serial Interface Functional Timing Transmit Byte Sync Functional Timing MII and Rmii Interfaces MII Transmit Half Duplex with a Collision Functional Timing FRAME# Rfsync RSYNC1 Rsync 2 RSYNC3 FRAME# RSYNC1 Rfsync RSYNC2 Rsync Rchclk RCHBLK1 Rsync RfsyncRchclk Rchblk Rsysclk Rser O Rchclk RCHBLK4 FRAME# TSYNC1 Tssync Tsync TSYNC3 Tchclk Tchblk Tchclk Tchblk 2,3 12.4 E1 Mode FRAME# Rfsync Rsync Rsysclk Rsero RSYNC2 Rmsync RSYNC3 Rchclk RchblkRmsync Rsync Rchclk RCHBLK3 FRAME# TSYNC1 Tssync Rsync Tsync Rchclk Tchclk Rchblk TchblkTSYNC2 26. Transmit-Side Boundary Timing Elastic Store Disabled Tssync Tchclk Tchblk 312 Parameter Symbol Conditions MIN TYP MAX Units DC Electrical CharacteristicsRecommended DC Operating Conditions Thermal Characteristics -3. Thermal Characteristics Theta-JA vs. AirflowParameter MIN TYP MAX AIR Flow THETA-JA Parameter Symbol MII Interface Transmit MII Interface10Mbps 100Mbps MIN TYP MAX Receive MII Interface Receive MII Interface Timing Rmii Interface Transmit Rmii Interface Transmit Rmii Interface Timing Receive Rmii Interface Receive Rmii Interface Timing Mdio Interface Parameter Symbol MIN TYP MAX UnitsMDC Mdio Transmit WAN Interface 10. Transmit WAN Interface Tclke Tsero Tden Tbsync Receive WAN Interface 11. Receive WAN Interface Rclki Rseri Rden Rbsync Sdram Timing 12. Sdram Interface Timing 100 MHz Sdata RAS, ScasSWE, Sdcs SDA, SBA Parameter Symbol MIN TYP MAX Units Intel Bus Read Timing Modec = 11. Motorola Bus Read Timing Modec = RCHBLK, Rfsync RMSYNC, Rsync Rsero / Rdata / Rsig Rfsync / Rmsync See Note Rsero / RsigRchblk Rmsync Rsync 15. Receive Line Interface Timing 16. Receive Timing Delay Rclko to Bpclk Delay Rclko to Bpclk Parameter Symbol Conditions MIN TYP E1 MAX Units TSERI, TSIG, TDATA, TPOSI, Tnegi 17. Transmit-Side Timing 18. Transmit-Side Timing, Elastic Store Enabled 20. Jtag Interface Timing Diagram Jtag Interface Timing 17. Jtag Interface Timing Jtag Information Jtag TAP Controller State Machine Description Update-DR Update-IRSelect-IR-Scan Capture-IR TAP Controller State Diagram Instruction Register Instruction Codes for Ieee 1149.1 Architecture Instruction Selected Register Instruction Codes Jtag ID Codes ID Code Structure Test RegistersBoundary Scan Register Bypass Register Jtag Functional Timing Bypass Idcode State Package Information 15.1 256-Ball BGA 27mm x 27mm 56-G6004-001 Document Revision History Revision Description