DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver

Register Name:

TR.TCBR1

Register Description:

Transmit Channel Blocking Register 1

Register Address:

8Ch

Bit #

Name

Default

7

6

5

4

3

2

1

0

CH8

CH7

CH6

CH5

CH4

CH3

CH2

CH1

0

0

0

0

0

0

0

0

Bits 0 – 7: Transmit Channels 1 to 8 Channel Blocking Control Bits (CH1 to CH8) 0 = force the TCHBLK pin to remain low during this channel time

1 = force the TCHBLK pin high during this channel time

Register Name:

TR.TCBR2

Register Description:

Transmit Channel Blocking Register 2

Register Address:

8Dh

Bit #

Name

Default

7

6

5

4

3

2

1

0

CH16

CH15

CH14

CH13

CH12

CH11

CH10

CH9

0

0

0

0

0

0

0

0

Bits 0 – 7: Transmit Channels 9 to 16 Channel Blocking Control Bits (CH9 to CH16) 0 = force the TCHBLK pin to remain low during this channel time

1 = force the TCHBLK pin high during this channel time

Register Name:

TR.TCBR3

Register Description:

Transmit Channel Blocking Register 3

Register Address:

8Eh

Bit #

Name

Default

7

6

5

4

3

2

1

0

CH24

CH23

CH22

CH21

CH20

CH19

CH18

CH17

0

0

0

0

0

0

0

0

Bits 0 – 7: Transmit Channels 17 to 24 Channel Blocking Control Bits (CH17 to CH24) 0 = force the TCHBLK pin to remain low during this channel time

1 = force the TCHBLK pin high during this channel time

Register Name:

TR.TCBR4

Register Description:

Transmit Channel Blocking Register 4

Register Address:

8Fh

Bit #

Name

Default

7

6

5

4

3

2

1

0

CH32

CH31

CH30

CH29

CH28

CH27

CH26

CH25

0

0

0

0

0

0

0

0

Bits 0 – 7: Transmit Channels 25 to 32 Channel Blocking Control Bits (CH25 to CH32) 0 = force the TCHBLK pin to remain low during this channel time

1 = force the TCHBLK pin high during this channel time

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Image 264
Maxim DS33R11 specifications TR.TCBR1, TR.TCBR2, TR.TCBR3, TR.TCBR4