Maxim DS33R11 specifications Tr.Escr, Elastic Store Control Register, 4Fh

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver

Register Name:		TR.ESCR
Register Description:		Elastic Store Control Register
Register Address:		4Fh
Bit #	7	6	5	4	3	2	1	0
Name	TESALGN	TESR	TESMDM	TESE	RESALGN	RESR	RESMDM	RESE
Default	0	0	0	0	0	0	0	0

Bit 7: Transmit Elastic Store Align (TESALGN). Setting this bit from a 0 to a 1 forces the transmit elastic store’s write/read pointers to a minimum separation of half a frame. No action is taken if the pointer separation is already greater or equal to half a frame. If pointer separation is less than half a frame, the command is executed and the data is disrupted. It should be toggled after TSYSCLK has been applied and is stable. It must be cleared and set again for a subsequent align. See Section 10.12.3 for details.

Bit 6: Transmit Elastic Store Reset (TESR). Setting this bit from a 0 to a 1 forces the read and write pointers into opposite frames, maximizing the delay through the transmit elastic store. Transmit data is lost during the reset. It should be toggled after TSYSCLK has been applied and is stable. See Section 10.12.3 for details. Do not leave this bit set HIGH.

Bit 5: Transmit Elastic Store Minimum-Delay Mode (TESMDM). See Section 10.12.4 for details. 0 = elastic stores operate at full two-frame depth

1 = elastic stores operate at 32-bit depth

Bit 4: Transmit Elastic Store Enable (TESE) 0 = elastic store is bypassed

1 = elastic store is enabled

Bit 3: Receive Elastic Store Align (RESALGN). Setting this bit from a 0 to a 1 forces the receive elastic store’s write/read pointers to a minimum separation of half a frame. No action is taken if the pointer separation is already greater or equal to half a frame. If pointer separation is less than half a frame, the command is executed and the data is disrupted. It should be toggled after RSYSCLK has been applied and is stable. Must be cleared and set again for a subsequent align. See Section 10.12.3 for details.

Bit 2: Receive Elastic Store Reset (RESR). Setting this bit from a 0 to a 1 forces the read and write pointers into opposite frames, maximizing the delay through the receive elastic store. It should be toggled after RSYSCLK has been applied and is stable. See Section 10.12.3 for details. Do not leave this bit set HIGH.

Bit 1: Receive Elastic Store Minimum-Delay Mode (RESMDM). See Section 10.12.4 for details. 0 = elastic stores operate at full two-frame depth

1 = elastic stores operate at 32-bit depth

Bit 0: Receive Elastic Store Enable (RESE) 0 = elastic store is bypassed

1 = elastic store is enabled

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