Maxim DS33R11 specifications Li.Thpmuu, Li.Thpmus

	DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
Register Name:	LI.THPMUU
Register Description:	Serial Interface Transmit HDLC PMU Update Register
Register Address:	0D6h

Bit #

Name

Default

7	6	5	4
-	-	-	-
0	0	0	0

3

-

0

2	1	0
-	-	TPMUU
0	0	0

Bit 0: Transmit PMU Update (TPMUU) This signal causes the transmit cell/packet processor block performance monitoring registers (counters) to be updated. A 0 to 1 transition causes the performance monitoring registers to be updated with the latest data, and the counters reset (0 or 1). This update updates performance monitoring counters for the Serial Interface.

Register Name:	LI.THPMUS
Register Description:	Serial Interface Transmit HDLC PMU Update Status Register
Register Address:	0D7h

Bit #

Name

Default

7	6	5	4
-	-	-	-
0	0	0	0

3

-

0

2	1	0
-	-	TPMUS
0	0	0

Bit 0: Transmit PMU Update Status (TPMUS) This bit is set when the Transmit PMU Update is completed. This bit is cleared when TPMUU is reset.

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