Maxim DS33R11 Figure 13-16. Receive Timing Delay RCLKO to BPCLK

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
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13.10 AC Characteristics: Backplane Clock Timing
Table 13-15. AC Characteristics: Backplane Clock Synthesis
(VDD = 3.3V ±5%, TA = -40°C to +85°C.) (Note 1, (Figure 13-16)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Delay RCLKO to BPCLK tD1 10 ns
Note: Timing parameters in this table are guaranteed by design (GBD).
Figure 13-16. Receive Timing Delay RCLKO to BPCLK
tD1
BPCLK
RCLKO
NOTE: IF RCLKO IS 1.544 MHZ, BPCLK WILL BE ASYNCHRONOUS.