Maxim DS33R11 specifications Jtag Functional Timing, Bypass Idcode State

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver

14.5 JTAG Functional Timing

This functional timing for the JTAG circuits shows:

•The JTAG controller starting from reset state.

•Shifting out the first 4 LSB bits of the IDCODE.

•Shifting in the BYPASS instruction (111) while shifting out the mandatory X01 pattern.

•Shifting the TDI pin to the TDO pin through the bypass shift register.

•An asynchronous reset occurs while shifting.

Figure 14-3. JTAG Functional Timing

(INST)

IDCODE

BYPASS

IDCODE

(STATE)

Reset

Run Test

Select DR

Capture

Shift

Exit1

Update

Select DR

Select IR

Capture

Shift IR

Exit1

Update

Select DR

Capture

Shift

Test

Idle

Scan

DR

DR

DR

DR

Scan

Scan

IR

IR

IR

Scan

DR

DR

Logic Idle

JTCLK

JTRST

JTMS

X

X

JTDI

X

X

X

JTDO

X

Output

Output pin level change if in "EXTEST" instruction mode

Pin

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