10.1 T1/E1/J1 Clocks, T1/E1/J1 Clock Map | Maxim DS33R11 specification

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver

10 INTEGRATED T1/E1/J1 TRANSCEIVER

10.1 T1/E1/J1 Clocks

Figure 10-1 shows the clock map of the T1/E1 transceiver. The routing for the transmit and receive clocks are shown for the various loopback modes and jitter attenuator positions. Although there is only one jitter attenuator, which can be placed in the receive or transmit path, two are shown for simplification and clarity.

Figure 10-1. T1/E1/J1 Clock Map
MCLK
								TSYSCLK
MCLKS = 0	MCLKS = 1
PRE-SCALER		TR.LIC4.MPS0
		TR.LIC4.MPS1
2.048 TO 1.544		TR.LIC2.3
SYNTHESIZER
					DJA = 1
						8 x PLL			8XCLK
	LOCAL	JITTER ATTENUATOR			DJA = 0
	LOCAL	JITTER ATTENUATOR
	LOOPBACK	SEE TR.LIC1		REMOTE	FRAMER	PAYLOAD
		REGISTER		REMOTE	FRAMER	PAYLOAD
		REGISTER		LOOPBACK	LOOPBACK	LOOPBACK
RCL = 1			JAS = 0	LOOPBACK	LOOPBACK	LOOPBACK
RCL = 1	LLB = 0		JAS = 0			(SEE NOTES)	BPCLK
			AND			(SEE NOTES)			BPCLK
			AND
RXCLK		LTCA	DJA = 0		FLB = 0		SYNTH
RXCLK		LTCA			FLB = 0	RECEIVE
RCL = 0	LLB = 1					RECEIVE			RCLK
	LLB = 1		JAS = 1			FRAMER			RCLK
TO			JAS = 1		FLB = 1
TO		JAS = 0	OR		FLB = 1
LIU		JAS = 0	DJA = 1
		OR
		DJA = 1		RLB = 1
TXCLK				RLB = 1		PLB = 1
						PLB = 1
			LTCA			TRANSMIT
			LTCA			TRANSMIT
		JAS = 1		RLB = 0		FORMATTER
		AND		RLB = 0		PLB = 0
		DJA = 0				PLB = 0
		DJA = 0
								TCLKT
								MUX
						A	B	C	TCLKT
									TCLKT

The TCLKT MUX is dependent on the state of the TCSS0 and TCSS1 bits in the TR.CCR1 register and the state of the TCLKT pin.

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Maxim DS33R11 specifications 10.1 T1/E1/J1 Clocks, T1/E1/J1 Clock Map

Contents

DS33R11 Part Temp Range PIN-PACKAGE Table of Contents Integrated T1/E1/J1 Transceiver Device Registers Operating Parameters List of Figures 308 List of Tables Description Page X.86 Link Access Protocol for SONET/SDH Ethernet Mapping GeneralMicroprocessor Interface Hdlc Ethernet Mapping Committed Information Rate CIR Controller Sdram InterfaceMAC Interface T1/E1/J1 Line Interface Clock SynthesizerJitter Attenuator 12 T1/E1/J1 Framer TDM Bus Test and Diagnostics Specifications Compliance T1-Related Telecommunications Specifications Ethernet-to-WAN Extension With or Without Framing B8ZS BOCCRC ESF Major Operating Modes Clad Ttip Transmit Framer MUX Tring BertRtip Rring MUX JTAG2 Transmit Serial Port Packet HDLC/X.86 CIR Controller Clock Jtag Host Interface Receive and Transmit T1/E1/J1 LIU Data Loopback Sync Framer Sync Rsync Rmsync Rfsync Internal Rdata Signals Rchclk From Sync Signaling Tseri TsigRlink Rlclk Pin Functional Description Detailed Pin Descriptions Name PIN Type Function Microprocessor PortIOZ Read Data Strobe Intel Mode The DS33R11 drives the data bus Name PIN Type FunctionChip Select for Protocol Conversion Device This pin must be Name PIN Type Function MII/RMII PHY Port Receive Data 0 through 3 MII Four bits of received dataReceive Data 0 through 1 Rmii Two bits of received data Reference Clock Rmii and MII When in Rmii mode, all signals Transmit Data 0 through 3MII TXD 30 is presentedTransmit Data 0 through 1RMII Two bits of data TXD Reference Clock Output Rmii and MII a derived clock output Name PIN Type Function PHY Management BUS Sdram InterfaceSdcs Sdram Data Bus Bits 0 to 31 The 32 pins of the Sdram data Name PIN Type Function T1/E1/J1 Analog Line Interface T1/E1/J1 Transmit Framer Interface Ethernet Mapper Transmit Serial Interface T1/E1/J1 Receive Framer Interface Receive System Clock for the Transceiver 1.544MHz Receive Frame Sync Pre Receive Elastic Store for T1/E1/J1Receive Multiframe Sync for the T1/E1/J1 Transceiver An T1/E1/J1 FRAMER/LIU Interim Signals Transmit Negative-Data Output Updated on the rising edge Transmit Positive-Data Output Updated on the rising edgeTransmit Elastic Store Output Updated on the rising edge Transmit Clock Output from the T1/E1/J1 Framer Buffered Name PIN Type Function Hardware and Status Pins Mode Control for Processor InterfaceT1/E1/J1 Receive Signaling-Freeze Output Set high when Queue Overflow for Ethernet Mapper This pin goes high when Name PIN Type Function System Clocks Name PIN Type Function Jtag Interface Name PIN Type Function Power Supplies Receive Analog Positive Supply Connect to 3.3V power supplyReceive Analog Signal Ground Connect to the common supply Transmit Analog Signal Ground Connect to the common supply Ball BGA Pinout Functional Description Processor Interface Read-Write/Data Strobe ModesClear on Read Interrupt and Pin Modes Ethernet Mapper Clocks Clocking Options for the Ethernet InterfaceRmiimiis Speed DCE/ DTE Refclko Rxclk PIN Output Input Txclk T1/E1/J1 Ethernet MACBert Refclk Arbiter Ethernet Interface Clock Modes Serial Interface Clock Modes Resets and Low Power Modes Reset FunctionsReset Function Location Comments Initialization and Configuration Global ResourcesPer-Port Resources Example Device Initialization Sequence Device Interrupts Drawing Legend Pin Interrupt Information Registers Status RegistersInformation Registers Serial Interface Connections and Queues Registers Related to Connections and Queues ArbiterRegister Function Type Mode Flow ControlOptions for Flow Control Full Duplex Flow Control Half Duplex Flow Control Host-Managed Flow Control Ethernet Interface Port Ieee 802.3 Ethernet Frame Registers Related to Setting the Ethernet Port Register Name Function Configured as DTE Connected to an Ethernet PHY in MII Mode DTE and DCE Mode DS33R11 Configured as a DCE in MII Mode Ethernet MAC MAC Control Registers MAC Status RegistersAddress Register Description MII Mode Options Rmii Mode Bert Features Bert in the Ethernet MapperPHY MII Management Block and Mdio Interface Receive Data Interface Receive Pattern DetectionPrbs Synchronization Repetitive Pattern Synchronization Pattern MonitoringPattern Generation Error Insertion Performance Monitoring UpdateTransmit Packet Processor Receive Packet Processor 11. Hdlc Encapsulation of MAC Frame 19 X.86 Encoding and Decoding 12. Laps Encoding of MAC Frames Concept 13. X.86 Encapsulation of the MAC frame Page Committed Information Rate Controller 10.1 T1/E1/J1 Clocks T1/E1/J1 Clock Map T1/E1/J1 Transmit Clock Source Per-Channel Operation10.3 T1/E1/J1 Transceiver Interrupts TCSS1 TCSS0 Transmit Clock Source 10.4 T1 Framer/Formatter Control and Status 10.4.1 T1 Transmit TransparencyAIS-CI and RAI-CI Generation and Detection T1 Alarm Criteria Alarm SET Criteria Clear Criteria10.4.3 T1 Receive-Side Digital-Milliwatt Code Generation 10.5 E1 Framer/Formatter Control and Status E1 Sync/Resync CriteriaFrame or Sync Criteria Resync Criteria Multiframe Level ITU Spec E1 Alarm Criteria Automatic Alarm GenerationAlarm SET Criteria Clear Criteria ITU Specification Per-Channel Loopback Error Counters T1 Line Code Violation Counting OptionsE1 Line-Code Violation Counting Options Line-Code Violation Counter TR.LCVCR Framing Mode T1 Path Code Violation Counting ArrangementsPath Code Violation Count Register TR.PCVCR Counted T1 Frames Out-of-Sync Counting Arrangements Frames Out-of-Sync Count Register TR.FOSCRBit Counter TR.EBCR 10.8 DS0 Monitoring Function Signaling Operation Processor-Based Receive SignalingChange-of-State Hardware-Based Receive Signaling Receive Signaling Reinsertion at RseroForce Receive Signaling All Ones Receive Signaling Freeze Processor-Based Transmit Signaling 10.9.3.1 T1 Mode Hardware-Based Transmit Signaling 10.9.3.2 E1 ModeTime Slot Numbering Schemes Channel Phone Per-Channel Idle Code Generation 10. Idle-Code Array Address MappingBits 0 to 5 of Iaar Maps to Channel Idle-Code Programming Examples Example 10.12.1.1 T1 Mode 10.12.1.2 E1 ModeChannel Blocking Registers Elastic Stores Operation 11. Elastic Store Delay After Initialization Minimum Delay ModeInitialization Register BIT Delay Transmit Elastic Store 10.13 G.706 Intermediate CRC-4 Updating E1 Mode Only CRC-4 Recalculate Method 10.14 T1 Bit-Oriented Code BOC Controller Transmit BOCReceive BOC Transmit a BOC Additional Sa and International Si Bit Operation E1 Only Method 1 Internal Register Scheme Based on Double-FrameMethod 2 Internal Register Scheme Based on CRC4 Multiframe Hdlc Configuration Additional Hdlc Controllers in T1/E1/J1 Transceiver 12. Hdlc Controller Registers Fifo Control Hdlc MappingRegister Channels Fifo Information Receive Packet-Bytes AvailableReceive Hdlc Code Example Legacy FDL Support T1 Mode OverviewReceive Section 10.18 D4/SLC-96 Operation Transmit Section Programmable In-Band Loop Code Generation and Detection Line Interface Unit LIU LIU OperationReceiver Receive Level Indicator and Threshold Interrupt Receive G.703 Synchronization Signal E1 ModeMonitor Mode T1/E1 Transmit BPV Error Insertion Transmit G.703 Synchronization Signal E1 ModeTransmitter Transmit Short-Circuit Detector/Limiter Mclk Prescaler CMI Code Mark Inversion OptionClock Data CMI 13. Transformer Specifications Specification Recommended ValueRecommended Circuits -7. Basic Interface DS33R11 E1 Transmit Pulse Template 10. Jitter Tolerance T1 Mode E1 Mode Bert Status Bert MappingXtald Mclk 15. Simplified Diagram of Bert in Network Direction Bert Error Counter Bert Repetitive Pattern SetBert Bit Counter Bert Alternating Word-Count Rate Payload Error-Insertion Function T1 Mode Only 14. Transmit Error-Insertion Setup Sequence15. Error Insertion Examples Number-of-Errors Registers Programmable Backplane Clock Synthesizer Fractional T1/E1 Support T1 Transmit 114 E1 Transmit E1 Transmit Flow Diagram 116 Register Address Map Mapper Chip Global Arbiter Bert Serial EthernetInterfac Port Select Registers Interface Transceiver Register Bit Maps Global Ethernet Mapper Register Bit MapGlobal Ethernet Mapper Register Bit Map Name Arbiter Register Bit Map Bert Register Bit MapArbiter Register Bit Map Bert Register Bit Map Serial Interface Register Bit Map Serial Interface Register Bit Map 114h Ethernet Interface Register Bit Map Ethernet Interface Register Bit Map MAC Indirect Register Bit Map MAC Register Bit Map 200h T1/E1/J1 Transceiver Register Bit Map Active when CST = 019 01A 035 050 06A 085 0AA 0AB0AC 0AD 0CA 0CB0CC 0CD 0DC 0DD0DE 0DF Global Register Definitions for Ethernet Mapper GL.IDRLGL.IDRH GL.CR1 GL.BLR GL.RTCAL GL.SRCALSGL.LIE GL.LIS GL.SIEGL.SIS GL.TRQIE GL.TRQISGL.BIE GL.BIS GL.CON1 GL.C1QPR GL.BISTEN GL.BISTPF GL.SDMODE1 GL.SDMODE2 GL.SDMODEWSGL.SDRFTC Arbiter Registers Arbiter Register Bit DescriptionsAR.RQSC1 AR.TQSC1 Bert Registers BCRBert Control Register 80h Bpclr Bpchr BSPB0R BSPB1RBSPB2R BSPB3R Teicr BSR Bsrl Bsrie RBECB0R RBECB1RRBECR2 RBCB0 RBCB1 RBCB2RBCB3 Serial Interface Registers Serial Interface Transmit and Common RegistersLI.TSLCR LI.RSTPD LI.LPBK LI.TPPCL LI.TIFGC LI.TEPLC Transmit Errored Packet High Control Register Cleanup routineLI.TEPHC 0C7h LI.TPPSR LI.TPPSRLLI.TPPSRIE LI.TPCR0 LI.TPCR1LI.TPCR2 LI.TBCR0 LI.TBCR1LI.TBCR2 LI.TBCR3 LI.THPMUU LI.THPMUS 11.5.2 X.86 Registers LI.TX86EDELI.TRX86A LI.TRX8C LI.TRX86SAPIL LI.CIR Receive Serial Interface LI.RSLCRLI.RPPCL LI.RMPSCL LI.RMPSCHLI.RPPSR LI.RPPSRL Receive Packet Processor Status Register Latched105h Repl Rapl Ripdl Rspdl Rlpdl Repcl Rapcl Rspcl Receive Packet Processor Status Register Interrupt Enable LI.RPPSRIE106h Repie Rapie Ripdie Rspdie Rlpdie Repcie Rapcie Rspcie LI.RPCB0 LI.RPCB1LI.RPCB2 LI.RFPCB0 LI.RFPCB1LI.RFPCB2 LI.RAPCB0 LI.RAPCB1LI.RAPCB2 LI.RSPCB0 LI.RSPCB1LI.RSPCB2 LI.RBC0 LI.RBC1LI.RBC2 LI.RBC3 LI.RAC0 LI.RAC1LI.RAC2 LI.RAC3 LI.RHPMUU LI.RHPMUSLI.RX86S LI.RX86LSIE LI.TQLTLI.TQHT LI.TQTIE 126hLI.TQCTLS 127h Ethernet Interface Registers Ethernet Interface Register Bit DescriptionsSU.MACRADL SU.MACRADH SU.MACRD1 SU.MACRD2SU.MACRD3 SU.MACWD0 SU.MACWD1 SU.MACWD2SU.MACWD3 SU.MACAWL SU.MACAWH SU.MACRWC SU.LPBK SU.GCR SU.TFRC Transmit Frame Resend Control151h Ncfq Tprhbc Tprcb SU.TFSL SU.TFSH SU.RFSB0 SU.RFSB1SU.RFSB2 SU.RFSB3 157hMCF SU.RMFSRL SU.RMFSRHSU.RQLT SU.RQHT SU.QRIE SU.QCRLS SU.RFRC Receive Frame Rejection Control15Eh Ucfr Cfrr Lerr Crcerr DBR Miier BFR MAC Registers SU.MACCR Bit Random Number Generator Bits Used SU.MACMIIA SU.MACMIID SU.MACFCR SU.MMCCTRL Reserved MAC Reserved Control Register010Ch indirect 010Dh 0110h indirect 0111h0112h 0113h SU.RxFrmCtr MAC All Frames Received Counter0200h indirect 0201h SU.RxFrmOkCtr MAC Frames Received OK Counter0204h indirect 0205h SU.TxFrmCtr MAC All Frames Transmitted Counter0300h indirect 0301h SU.TxBytesCtr MAC All Bytes Transmitted Counter0308h indirect 0309h SU.TxBytesOkCtr MAC Bytes Transmitted OK Counter030Ch indirect 030Dh SU.TxFrmUndr MAC Transmit Frame Under Run Counter0334h indirect 0335h SU.TxBdFrmCtr MAC All Frames Aborted Counter0338h indirect 0339h Master Mode Register Effect On Output Pins11.7 T1/E1/J1 Transceiver Registers TR.MSTRREG Configuration Register Bit 6 Rsync Mode Select 2 RSMS2TR.IOCR1 Bit 1 Tsync I/O Select Tsio 0 = Tsync is an input TR.IOCR2 TR.T1RCR1 OOF2 OOF1 Bit 6 Receive Frame Mode Select RFM 0 = D4 framing mode Bit 5 Receive B8ZS Enable RB8ZSBit 1 Receive Japanese CRC6 Enable RJC TR.T1RCR2 TR.T1TCR1 Bit 7 Transmit B8ZS Enable TB8ZS TR.T1TCR2TB8ZS TSLC96 Tzse FBCT2 FBCT1 TD4YM TB7ZS Bit 2 Transmit Frame Mode Select TFM 0 = D4 framing mode TR.SSIE1 T1 ModeTR.T1CCR1 T1 Common Control Register TR.SSIE1 E1 Mode Software Signaling Insertion EnableTR.SSIE2 E1 Mode TR.SSIE3 E1 Mode LcawTR.SSIE4 TR.T1RDMR1 TR.T1RDMR2TR.T1RDMR3 TR.IDR TR.INFO1 TR.INFO2 11hBits 0 3 Receive Level Bits RL0 to RL3. Real-time bits RL3 RL2 RL1 RL0 TR.INFO3 TR.IIR1TR.IIR2 Ilut Timer Rscos Jalt Lrcl Tcle Tocd Lolitc TR.SR1Status Register 16h TR.IMR1 Interrupt Mask Register17h Bit 7 Input Level Under Threshold Ilut 0 = interrupt masked TR.SR2 18hRyelc RUA1C Frclc Rlosc TR.IMR2 19hBit 0 Receive Loss-of-Sync Condition Rlos TR.SR3 1AhLspare LDN LUP Lotc Lorc V52LNK Rdma RRA TR.IMR3 TR.SR4 1ChRAIS-CI Rsao Rsaz TMF TAF RMF Rcmf RAF Bit 2 Receive Multiframe Event RMF TR.IMR4 1DhBit 7 Receive AIS-CI Event RAIS-CI Bit 3 Transmit Align Frame Event TAF 0 = interrupt masked TR.SR5 1EhTesf Tesem Tslip Resf Resem Rslip TR.IMR5 1Fh TR.SR6, TR.SR7 Hdlc #1 Status RegisterHdlc #2 Status Register 20h, 22h TR.IMR6, TR.IMR7 TR.INFO5, TR.INFO6 PS2 PS1 PS0TR.INFO4 TR.SR8 TR.IMR8 TR.SR9 26hBbed Bbco BEC0 BRA1 BRA0 Brlos Bsync TR.IMR9 TR.PCPR Per-Channel Pointer Register28h Rsaoics Rsrcs Rfcs Brcs Thscs Peics Tfcs Btcs TR.PCDR1 TR.PCDR2TR.PCDR3 TR.PCDR4 TR.INFO7 TR.H1RC, TR.H2RCHdlc #1 Receive Control Hdlc #2 Receive Control 31h, 32h TR.E1RCR1 TR.E1RCR2 TR.E1TCR1 TR.E1TCR2 TR.BOCCRBF1 RBF0 TR.RSINFO1, TR.RSINFO2, TR.RSINFO3, TR.RSINFO4 MSB LSBTR.RSCSE1, TR.RSCSE2, TR.RSCSE3, TR.RSCSE4 Signaling Control Register TR.SIGCRGrsre RFE RFF Rccs Tccs Frsao Error-Counter Configuration Register Bit 5 Error-Counter Update Select EcusBit 4 Error-Accumulation Mode Select Eams Bit 2 Pcvcr Fs-Bit Error-Report Enable Fsbe TR.LCVCR1 TR.LCVCR2TR.PCVCR1 TR.PCVCR2 TR.FOSCR1 TR.FOSCR2TR.EBCR1 TR.EBCR2 TR.LBCR Loopback Control Register4Ah Liuc LLB RLB PLB FLB TR.PCLR1 TR.PCLR2TR.PCLR3 TR.PCLR4 TR.ESCR Elastic Store Control Register4Fh Tesalgn Tesr Tesmdm Tese Resalgn Resr Resmdm Rese Transmit Signaling Registers E1 Mode, CAS Format TR.TS1 to TR.TS1650h to 5Fh Transmit Signaling Registers E1 Mode, CCS Format Transmit Signaling Registers T1 Mode, ESF Format TR.TS1 to TR.TS1250h to 5Bh Transmit Signaling Registers T1 Mode, D4 Format CH2-A CH2-BCH1-A CH1-B CH4-A CH4-B Receive Signaling Registers T1 Mode, ESF Format Receive Signaling Registers T1 Mode, D4 FormatTR.RS1 to TR.RS12 60h to 6Bh Receive Signaling Registers E1 Mode, CAS Format Receive Signaling Registers E1 Mode, CCS FormatTR.RS1 to TR.RS16 60h to 6Fh TR.CCR1 TCSS1 TCSS0 TR.CCR2 BPCS1 BPCS0TR.CCR3 TR.CCR4 RLT3 RLT2 RLT1 RLT0TR.TDS0SEL TR.TDS0M TR.RDS0SELTR.RDS0M TR.LIC1 Bit 6 Automatic Gain Control Enable Agce Network Mode GC5 GC4 GC3 GC2 GC1 GC0TR.TLBC T1, Impedance Match Off TR.LIC2 79hETS Lirst Ibpv TUA1 Jamux Scld Clds Bit 7 E1/T1 Select ETS TR.LIC3 MM1 MM0 TR.LIC4 MPS1 MPS0 JamuxMclk MPS1 MPS0 Jamux TT1 TT0 TR.IAAR Gric Gtic FunctionTR.PCICR TR.TCICE1 TR.TCICE2 TR.TCICE3TR.TCICE4 TR.RCICE1 TR.RCICE2 TR.RCICE3TR.RCICE4 TR.RCBR1 TR.RCBR2 TR.RCBR3TR.RCBR4 TR.TCBR1 TR.TCBR2TR.TCBR3 TR.TCBR4 TR.H1TC, TR.H2TC Hdlc #1 Transmit ControlHdlc #2 Transmit Control 90h, A0h TR.H1FC, TR.H2FC TFLWM2 TFLWM1 TFLWM0RFHWM2 RFHWM1 RFHWM0 Register Name TR.H1RCS1, TR.H1RCS2, TR.H1RCS3, TR.H1RCS4 A2h, A3h, A4h, A5hBit 3 Receive Hdlc Channel Select Bit Bit 2 Receive Hdlc Channel Select Bit TR.H1RTSBS, TR.H2RTSBS Hdlc # 1 Receive Time Slot Bits/Sa Bits SelectHdlc # 2 Receive Time Slot Bits/Sa Bits Select 96h, A6h RCB8SE RCB7SE RCB6SE RCB5SE RCB4SE RCB3SE RCB2SE RCB1SE Register Name TR.H1TCS1, TR.H1TCS2, TR.H1TCS3, TR.H1TCS4 A7h, A8h, A9h, AAhBit 3 Transmit Hdlc Channel Select Bit Bit 2 Transmit Hdlc Channel Select Bit TR.H1TTSBS, TR.H2TTSBS TR.H1RPBA, TR.H2RPBA TR.H1TF, TR.H2TF TR.H1RF, TR.H2RF TR.H1TFBA, TR.H2TFBA TR.IBCCTC1 TC0 RUP2 RUP1 RUP0 TR.TCD1 TR.TCD2Transmit Code Definition Register B8h TR.RUPCD2 Receive Up-Code Definition RegisterBAh TR.RDNCD1 Receive Down-Code Definition RegisterBBh TR.RDNCD2 TR.RSCC In-Band Receive Spare Control RegisterBDh RSC2 RSC1 RSC0 TR.RSCD1 TR.RSCD2 TR.RFDL TR.BOCC.4 = Receive FDL RegisterC0h RBOC5 RBOC4 RBOC3 RBOC2 RBOC1 RBOC0 TR.TFDL TR.RFDLM1, TR.RFDLM2 TR.RAF Receive Align Frame RegisterC6h TR.RNAF TR.RSiAF Received Si Bits of the Align FrameC8h TR.RSiNAF TR.RRA TR.RSa5 Received Sa5 BitsCCh TR.RSa6 TR.RSa7 Received Sa7 BitsCEh TR.RSa8 TR.TAF TR.TNAF TR.TSiAF Transmit Si Bits of the Align FrameD2h TR.TSiNAF TR.TRA TR.TSa5 Transmitted Sa5 BitsD6h TR.TSa6 TR.TSa7 Transmit Sa7 BitsD8h TR.TSa8 TR.TSACR TR.BAWC TR.BRP1 TR.BRP2TR.BRP3 TR.BRP4 TR.BC1 PS1 PS0 TR.BC2 EIB2 EIB1 EIB0RPL3 RPL2 RPL1 RPL0 TR.BBC1 TR.BBC2TR.BBC3 TR.BBC4 TR.BEC1 EC7 EC6 EC5 EC4 EC3 EC2 EC1 EC0TR.BEC2 EC9 EC8 TR.BIC TR.ERC ER3 ER2 ER1 ER0 Number-of-Errors TR.NOE1ECh TR.NOE2 TR.NOEL1 TR.NOEL2 Functional Serial I/O Timing Tx Serial Interface Functional Timing Transmit Byte Sync Functional Timing MII and Rmii Interfaces MII Transmit Half Duplex with a Collision Functional Timing FRAME# Rfsync RSYNC1 Rsync 2 RSYNC3 FRAME# RSYNC1 Rfsync RSYNC2 Rsync Rsync Rfsync Rchclk RCHBLK1Rchclk Rchblk Rsysclk Rser O Rchclk RCHBLK4 FRAME# TSYNC1 Tssync Tsync TSYNC3 Tchclk Tchblk Tchclk Tchblk 2,3 12.4 E1 Mode FRAME# Rfsync Rsync Rsysclk Rsero RSYNC2 Rmsync RSYNC3 Rchclk RchblkRmsync Rsync Rchclk RCHBLK3 Rsync Tsync Rchclk Tchclk Rchblk Tchblk FRAME# TSYNC1 TssyncTSYNC2 26. Transmit-Side Boundary Timing Elastic Store Disabled Tssync Tchclk Tchblk 312 DC Electrical Characteristics Parameter Symbol Conditions MIN TYP MAX UnitsRecommended DC Operating Conditions Thermal Characteristics -3. Thermal Characteristics Theta-JA vs. AirflowParameter MIN TYP MAX AIR Flow THETA-JA Parameter Symbol MII Interface Transmit MII Interface10Mbps 100Mbps MIN TYP MAX Receive MII Interface Receive MII Interface Timing Rmii Interface Transmit Rmii Interface Transmit Rmii Interface Timing Receive Rmii Interface Receive Rmii Interface Timing Parameter Symbol MIN TYP MAX Units Mdio InterfaceMDC Mdio Transmit WAN Interface 10. Transmit WAN Interface Tclke Tsero Tden Tbsync Receive WAN Interface 11. Receive WAN Interface Rclki Rseri Rden Rbsync Sdram Timing 12. Sdram Interface Timing 100 MHz Sdata RAS, ScasSWE, Sdcs SDA, SBA Parameter Symbol MIN TYP MAX Units Intel Bus Read Timing Modec = 11. Motorola Bus Read Timing Modec = RCHBLK, Rfsync RMSYNC, Rsync Rsero / Rdata / Rsig Rfsync / Rmsync Rsero / Rsig See NoteRchblk Rmsync Rsync 15. Receive Line Interface Timing 16. Receive Timing Delay Rclko to Bpclk Delay Rclko to Bpclk Parameter Symbol Conditions MIN TYP E1 MAX Units TSERI, TSIG, TDATA, TPOSI, Tnegi 17. Transmit-Side Timing 18. Transmit-Side Timing, Elastic Store Enabled 20. Jtag Interface Timing Diagram Jtag Interface Timing 17. Jtag Interface Timing Jtag Information Jtag TAP Controller State Machine Description Update-DR Update-IRSelect-IR-Scan Capture-IR TAP Controller State Diagram Instruction Register Instruction Codes for Ieee 1149.1 Architecture Instruction Selected Register Instruction Codes Jtag ID Codes ID Code Structure Test RegistersBoundary Scan Register Bypass Register Jtag Functional Timing Bypass Idcode State Package Information 15.1 256-Ball BGA 27mm x 27mm 56-G6004-001 Document Revision History Revision Description