DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver

Register Name:

 

 

GL.LIS

 

 

 

 

 

 

Register Description:

 

Global Serial Interface Interrupt Status

 

 

 

Register Address:

 

07h

 

 

 

 

 

 

Bit #

7

6

5

4

3

 

2

1

0

Name

 

 

-

-

 

-

LIN1TIS

-

 

-

-

LIN1RIS

Default

 

0

0

 

0

0

0

 

0

0

0

Bit 4: Serial Interface 1 TX Interrupt Status (LINE1TIS) This bit is set if Serial Interface 1 Transmit has an enabled interrupt generating event. Serial Interface interrupts consist of HDLC interrupts and X.86 interrupts.

Bit 0: Serial Interface 1 RX Interrupt Status (LINER1IS) This bit is set if Serial Interface 1 Receive has an enabled interrupt generating event. Serial Interface interrupts consist of HDLC interrupts and X.86 interrupts.

Register Name:

 

 

GL.SIE

 

 

 

 

 

 

Register Description:

 

Global Ethernet Interface Interrupt Enable

 

 

 

Register Address:

 

08h

 

 

 

 

 

 

Bit #

7

6

5

 

4

3

 

2

1

0

Name

 

 

-

-

 

-

 

-

-

 

-

-

SUB1IE

Default

 

0

0

 

0

 

0

0

 

0

0

0

Bit 0: Ethernet Interface 1 Interrupt Enable (SUB1IE)

Setting this bit to 1 enables an interrupt on SUB1S.

Register Name:

 

 

GL.SIS

 

 

 

 

 

 

 

Register Description:

 

Global Ethernet Interface Interrupt Status

 

 

 

 

Register Address:

 

09h

 

 

 

 

 

 

 

Bit #

7

6

5

 

4

3

 

2

 

1

0

Name

 

 

-

-

 

-

 

-

-

 

-

 

-

SUB1IS

Default

 

0

0

 

0

 

0

0

 

0

 

0

0

Bit 0: Ethernet Interface 1 Interrupt Status (SUB1IS)

This bit is set to 1 if Ethernet Interface 1 has an enabled

interrupt generating event. The Ethernet Interface consists of the MAC and The RMII/MII port.

 

 

137 of 344

Page 137
Image 137
Maxim DS33R11 specifications Gl.Lis, Gl.Sie, Gl.Sis