Maxim DS33R11 specifications 12 T1/E1/J1 Framer, TDM Bus

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver

2.12T1/E1/J1 Framer

•Fully independent transmit and receive functionality

•Full receive and transmit path transparency

•T1 framing formats include D4 (SLC-96) and ESF

•Detailed alarm and status reporting with optional interrupt support

•Large path and line error counters for:

oT1: BPV, CV, CRC6, and framing bit errors

oE1: BPV, CV, CRC4, E-bit, and frame alignment errors

•Timed or manual update modes

•DS1 idle code generation on a per-channel basis in both transmit and receive paths

oUser-defined

oDigital milliwatt

•ANSI T1.403-1998 Support

•RAI-CI detection and generation

•AIS-CI detection and generation

•E1 ETS 300 011 RAI generation

•G.965 V5.2 link detect

•Ability to monitor one DS0 channel in both the transmit and receive paths

•In-band repeating pattern generators and detectors

oThree independent generators and detectors

oPatterns from 1 to 8 bits or 16 bits in length

•RCL, RLOS, RRA, and RAIS alarms interrupt on change-of-state

•Flexible signaling support

oSoftware or hardware based

oInterrupt generated on change of signaling data

oReceive signaling freeze on loss-of-sync, carrier loss, or frame slip

•Addition of hardware pins to indicate carrier loss and signaling freeze

•Automatic RAI generation to ETS 300 011 specifications

•Access to Sa and Si bits

•Option to extend carrier loss criteria to a 1ms period as per ETS 300 233

•Japanese J1 support

oAbility to calculate and check CRC6 according to the Japanese standard

oAbility to generate Yellow Alarm according to the Japanese standard

2.13TDM Bus

•Dual two-frame independent receive and transmit elastic stores

oIndependent control and clocking

oControlled slip capability with status

oMinimum delay mode supported

•Programmable output clocks for fractional T1, E1, H0, and H12 applications

•Hardware signaling capability

oReceive signaling reinsertion to a backplane multiframe sync

oAvailability of signaling in a separate PCM data stream o Signaling freezing

•Ability to pass the T1 F-bit position through the elastic stores in the 2.048MHz backplane mode

•Access to the data streams in between the framer/formatter and the elastic stores

•User-selectable synthesized clock output

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