019 | Maxim DS33R11 manual

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver

Table 11-8. T1/E1/J1 Transceiver Register Bit Map (Active when CST = 0)

	ADD	NAME	BIT 7	BIT 6	BIT 5	BIT 4
	R
	000		—	—	—	—
	h	TR.MSTRREG

	001		RSMS	RSMS2	RSMS1	RSIO
	h	TR.IOCR1

	002		RDCLKIN	TDCLKIN	RSYNCINV	TSYNCINV
	h	TR.IOCR2	V	V

	003		—	ARC	OOF1	OOF2
	h	TR.T1RCR1

	004		—	RFM	RB8ZS	RSLC96
	h	TR.T1RCR2

	005		TJC	TFPT	TCPT	TSSE
	h	TR.T1TCR1

	006		TB8ZS	TSLC96	TZSE	FBCT2
	h	TR.T1TCR2

	007		—	—	—	TRAI-CI
	h	TR.T1CCR1

	008	TR.SSIE1-T1	CH8	CH7	CH6	CH5
	h	TR.SSIE1-E1	CH7	CH6	CH5	CH4
	009	TR.SSIE2-T1	CH16	CH15	CH14	CH13
	h	TR.SSIE2-E1	CH15	CH14	CH13	CH12
	00A	TR.SSIE3-T1	CH24	CH23	CH22	CH21
	h	TR.SSIE3-E1	CH22	CH21	CH20	CH19
	00B		CH30	CH29	CH28	CH27
	h	TR.SSIE4

	00C		CH8	CH7	CH6	CH5
	h	TR.T1RDMR1

	00D		CH16	CH15	CH14	CH13
	h	TR.T1RDMR2

	00E		CH24	CH23	CH22	CH21
	h	TR.T1RDMR3

	00F		ID7	ID6	ID5	ID4
	h	TR.IDR

	010		RPDV	TPDV	COFA	8ZD
	h	TR.INFO1

	011		BSYNC	BD	TCLE	TOCD
	h	TR.INFO2

	012		—	—	—	—
	h	TR.INFO3

	013		—	—	—	—
	h	Reserved

	014		SR8	SR7	SR6	SR5
	h	TR.IIR1

	015		—	—	—	—
	h	TR.IIR2

	016		ILUT	TIMER	RSCOS	JALT
	h	TR.SR1

	017		ILUT	TIMER	RSCOS	JALT
	h	TR.IMR1

	018		RYELC	RUA1C	FRCLC	RLOSC
	h	TR.SR2

	019	TR.IMR2	RYELC	RUA1C	FRCLC	RLOSC

BIT 3

TEST1

TSDW

TSSYNCINV

SYNCC

RZSE

GB7S

FBCT1

TAIS-CI

CH4

CH3

CH12

CH11

CH20

CH18

CH26

CH4

CH12

CH20

ID3

16ZD

RL3

—

—

SR4

—

LRCL

LRCL

RYEL

RYEL

BIT 2	BIT 1	BIT 0

TEST0	T1/E1	SFTRST

TSM	TSIO	ODF

H100EN	TSCLKM	RSCLKM

SYNCT	SYNCE	RESYNC

—	RJC	RD4YM

TFDLS	TBL	TYEL

TD4YM	Reserved	TB7ZS

TFM	PDE	TLOOP

CH3	CH2	CH1
CH2	CH1	UCAW
CH11	CH10	CH9
CH10	CH9	CH8
CH19	CH18	CH17
CH17	CH16	LCAW
CH25	CH24	CH23

CH3	CH2	CH1

CH11	CH10	CH9

CH19	CH18	CH17

ID2	ID1	ID0

SEFE	B8ZS	FBE

RL2	RL1	RL0

CRCRC	FASRC	CASRC

—	—	—

SR3	SR2	SR1

—	—	SR9

TCLE	TOCD	LOLITC

TCLE	TOCD	LOLITC

RUA1	FRCL	RLOS

RUA1	FRCL	RLOS

125 of 344

Image 125

Maxim DS33R11 specifications T1/E1/J1 Transceiver Register Bit Map Active when CST =, 019

Contents

Part Temp Range PIN-PACKAGE DS33R11 Table of Contents Integrated T1/E1/J1 Transceiver Device Registers Operating Parameters List of Figures 308 List of Tables Description Page General X.86 Link Access Protocol for SONET/SDH Ethernet MappingMicroprocessor Interface Hdlc Ethernet Mapping MAC Interface Committed Information Rate CIR ControllerSdram Interface Jitter Attenuator T1/E1/J1 Line InterfaceClock Synthesizer TDM Bus 12 T1/E1/J1 Framer Test and Diagnostics T1-Related Telecommunications Specifications Specifications Compliance Ethernet-to-WAN Extension With or Without Framing BOC B8ZSCRC ESF Major Operating Modes Bert Clad Ttip Transmit Framer MUX TringRtip Rring MUX JTAG2 Transmit Serial Port Packet HDLC/X.86 CIR Controller Jtag Host Interface Clock Receive and Transmit T1/E1/J1 LIU Loopback Sync Framer Data Sync Signaling Tseri Tsig Sync Rsync Rmsync Rfsync Internal Rdata Signals Rchclk FromRlink Rlclk IOZ Pin Functional Description Detailed Pin DescriptionsName PIN Type Function Microprocessor Port Chip Select for Protocol Conversion Device This pin must be Read Data Strobe Intel Mode The DS33R11 drives the data busName PIN Type Function Receive Data 0 through 1 Rmii Two bits of received data Name PIN Type Function MII/RMII PHY PortReceive Data 0 through 3 MII Four bits of received data Transmit Data 0 through 3MII TXD 30 is presented Reference Clock Rmii and MII When in Rmii mode, all signalsTransmit Data 0 through 1RMII Two bits of data TXD Reference Clock Output Rmii and MII a derived clock output Sdcs Name PIN Type Function PHY Management BUSSdram Interface Sdram Data Bus Bits 0 to 31 The 32 pins of the Sdram data T1/E1/J1 Transmit Framer Interface Name PIN Type Function T1/E1/J1 Analog Line Interface T1/E1/J1 Receive Framer Interface Ethernet Mapper Transmit Serial Interface Receive Multiframe Sync for the T1/E1/J1 Transceiver An Receive System Clock for the Transceiver 1.544MHzReceive Frame Sync Pre Receive Elastic Store for T1/E1/J1 T1/E1/J1 FRAMER/LIU Interim Signals Transmit Positive-Data Output Updated on the rising edge Transmit Negative-Data Output Updated on the rising edgeTransmit Elastic Store Output Updated on the rising edge Transmit Clock Output from the T1/E1/J1 Framer Buffered Mode Control for Processor Interface Name PIN Type Function Hardware and Status PinsT1/E1/J1 Receive Signaling-Freeze Output Set high when Queue Overflow for Ethernet Mapper This pin goes high when Name PIN Type Function System Clocks Name PIN Type Function Jtag Interface Receive Analog Positive Supply Connect to 3.3V power supply Name PIN Type Function Power SuppliesReceive Analog Signal Ground Connect to the common supply Transmit Analog Signal Ground Connect to the common supply Ball BGA Pinout Functional Description Read-Write/Data Strobe Modes Processor InterfaceClear on Read Interrupt and Pin Modes Clocking Options for the Ethernet Interface Ethernet Mapper ClocksRmiimiis Speed DCE/ DTE Refclko Rxclk PIN Output Input Txclk Bert Refclk Arbiter T1/E1/J1Ethernet MAC Serial Interface Clock Modes Ethernet Interface Clock Modes Reset Function Location Comments Resets and Low Power ModesReset Functions Global Resources Initialization and ConfigurationPer-Port Resources Example Device Initialization Sequence Device Interrupts Pin Drawing Legend Status Registers Interrupt Information RegistersInformation Registers Serial Interface Connections and Queues Register Function Registers Related to Connections and QueuesArbiter Options for Flow Control Type ModeFlow Control Full Duplex Flow Control Host-Managed Flow Control Half Duplex Flow Control Ieee 802.3 Ethernet Frame Ethernet Interface Port Register Name Function Registers Related to Setting the Ethernet Port DTE and DCE Mode Configured as DTE Connected to an Ethernet PHY in MII Mode Ethernet MAC DS33R11 Configured as a DCE in MII Mode Address Register Description MAC Control RegistersMAC Status Registers Rmii Mode MII Mode Options PHY MII Management Block and Mdio Interface Bert FeaturesBert in the Ethernet Mapper Prbs Synchronization Receive Data InterfaceReceive Pattern Detection Pattern Generation Repetitive Pattern SynchronizationPattern Monitoring Transmit Packet Processor Error InsertionPerformance Monitoring Update Receive Packet Processor 11. Hdlc Encapsulation of MAC Frame 12. Laps Encoding of MAC Frames Concept 19 X.86 Encoding and Decoding 13. X.86 Encapsulation of the MAC frame Page Committed Information Rate Controller T1/E1/J1 Clock Map 10.1 T1/E1/J1 Clocks Per-Channel Operation T1/E1/J1 Transmit Clock Source10.3 T1/E1/J1 Transceiver Interrupts TCSS1 TCSS0 Transmit Clock Source AIS-CI and RAI-CI Generation and Detection 10.4 T1 Framer/Formatter Control and Status10.4.1 T1 Transmit Transparency 10.4.3 T1 Receive-Side Digital-Milliwatt Code Generation T1 Alarm CriteriaAlarm SET Criteria Clear Criteria E1 Sync/Resync Criteria 10.5 E1 Framer/Formatter Control and StatusFrame or Sync Criteria Resync Criteria Multiframe Level ITU Spec Automatic Alarm Generation E1 Alarm CriteriaAlarm SET Criteria Clear Criteria ITU Specification Per-Channel Loopback T1 Line Code Violation Counting Options Error CountersE1 Line-Code Violation Counting Options Line-Code Violation Counter TR.LCVCR T1 Path Code Violation Counting Arrangements Framing ModePath Code Violation Count Register TR.PCVCR Counted Bit Counter TR.EBCR T1 Frames Out-of-Sync Counting ArrangementsFrames Out-of-Sync Count Register TR.FOSCR 10.8 DS0 Monitoring Function Change-of-State Signaling OperationProcessor-Based Receive Signaling Receive Signaling Reinsertion at Rsero Hardware-Based Receive SignalingForce Receive Signaling All Ones Receive Signaling Freeze 10.9.3.1 T1 Mode Processor-Based Transmit Signaling 10.9.3.2 E1 Mode Hardware-Based Transmit SignalingTime Slot Numbering Schemes Channel Phone 10. Idle-Code Array Address Mapping Per-Channel Idle Code GenerationBits 0 to 5 of Iaar Maps to Channel Example Idle-Code Programming Examples 10.12.1.2 E1 Mode 10.12.1.1 T1 ModeChannel Blocking Registers Elastic Stores Operation Minimum Delay Mode 11. Elastic Store Delay After InitializationInitialization Register BIT Delay Transmit Elastic Store CRC-4 Recalculate Method 10.13 G.706 Intermediate CRC-4 Updating E1 Mode Only Transmit BOC 10.14 T1 Bit-Oriented Code BOC ControllerReceive BOC Transmit a BOC Method 2 Internal Register Scheme Based on CRC4 Multiframe Additional Sa and International Si Bit Operation E1 OnlyMethod 1 Internal Register Scheme Based on Double-Frame Additional Hdlc Controllers in T1/E1/J1 Transceiver Hdlc Configuration 12. Hdlc Controller Registers Register Channels Fifo ControlHdlc Mapping Receive Hdlc Code Example Fifo InformationReceive Packet-Bytes Available Receive Section Legacy FDL Support T1 ModeOverview Transmit Section 10.18 D4/SLC-96 Operation Programmable In-Band Loop Code Generation and Detection Receiver Line Interface Unit LIULIU Operation Receive G.703 Synchronization Signal E1 Mode Receive Level Indicator and Threshold InterruptMonitor Mode T1/E1 Transmit G.703 Synchronization Signal E1 Mode Transmit BPV Error InsertionTransmitter Transmit Short-Circuit Detector/Limiter Clock Data CMI Mclk PrescalerCMI Code Mark Inversion Option Specification Recommended Value 13. Transformer SpecificationsRecommended Circuits -7. Basic Interface DS33R11 E1 Transmit Pulse Template 10. Jitter Tolerance E1 Mode T1 Mode Xtald Mclk Bert StatusBert Mapping 15. Simplified Diagram of Bert in Network Direction Bert Repetitive Pattern Set Bert Error CounterBert Bit Counter Bert Alternating Word-Count Rate 14. Transmit Error-Insertion Setup Sequence Payload Error-Insertion Function T1 Mode Only15. Error Insertion Examples Number-of-Errors Registers Fractional T1/E1 Support Programmable Backplane Clock Synthesizer T1 Transmit 114 E1 Transmit 116 E1 Transmit Flow Diagram Mapper Chip Global Arbiter Bert Serial Ethernet Register Address MapInterfac Port Select Registers Interface Transceiver Global Ethernet Mapper Register Bit Map Register Bit MapsGlobal Ethernet Mapper Register Bit Map Name Bert Register Bit Map Arbiter Register Bit MapArbiter Register Bit Map Bert Register Bit Map Serial Interface Register Bit Map Serial Interface Register Bit Map 114h Ethernet Interface Register Bit Map Ethernet Interface Register Bit Map MAC Register Bit Map MAC Indirect Register Bit Map 200h 019 T1/E1/J1 Transceiver Register Bit Map Active when CST = 01A 035 050 06A 085 0AB 0AA0AC 0AD 0CB 0CA0CC 0CD 0DD 0DC0DE 0DF GL.IDRH Global Register Definitions for Ethernet MapperGL.IDRL GL.BLR GL.CR1 GL.LIE GL.RTCALGL.SRCALS GL.SIS GL.LISGL.SIE GL.BIE GL.TRQIEGL.TRQIS GL.CON1 GL.BIS GL.BISTEN GL.C1QPR GL.SDMODE1 GL.BISTPF GL.SDRFTC GL.SDMODE2GL.SDMODEWS Arbiter Register Bit Descriptions Arbiter RegistersAR.RQSC1 AR.TQSC1 BCR Bert RegistersBert Control Register 80h Bpchr Bpclr BSPB1R BSPB0RBSPB2R BSPB3R BSR Teicr Bsrie Bsrl RBECB1R RBECB0RRBECR2 RBCB0 RBCB3 RBCB1RBCB2 Serial Interface Transmit and Common Registers Serial Interface RegistersLI.TSLCR LI.RSTPD LI.TPPCL LI.LPBK LI.TEPLC LI.TIFGC Cleanup routine Transmit Errored Packet High Control RegisterLI.TEPHC 0C7h LI.TPPSRIE LI.TPPSRLI.TPPSRL LI.TPCR2 LI.TPCR0LI.TPCR1 LI.TBCR1 LI.TBCR0LI.TBCR2 LI.TBCR3 LI.THPMUS LI.THPMUU LI.TX86EDE 11.5.2 X.86 RegistersLI.TRX86A LI.TRX8C LI.CIR LI.TRX86SAPIL LI.RPPCL Receive Serial InterfaceLI.RSLCR LI.RPPSR LI.RMPSCLLI.RMPSCH Receive Packet Processor Status Register Latched LI.RPPSRL105h Repl Rapl Ripdl Rspdl Rlpdl Repcl Rapcl Rspcl LI.RPPSRIE Receive Packet Processor Status Register Interrupt Enable106h Repie Rapie Ripdie Rspdie Rlpdie Repcie Rapcie Rspcie LI.RPCB2 LI.RPCB0LI.RPCB1 LI.RFPCB2 LI.RFPCB0LI.RFPCB1 LI.RAPCB2 LI.RAPCB0LI.RAPCB1 LI.RSPCB2 LI.RSPCB0LI.RSPCB1 LI.RBC1 LI.RBC0LI.RBC2 LI.RBC3 LI.RAC1 LI.RAC0LI.RAC2 LI.RAC3 LI.RX86S LI.RHPMUULI.RHPMUS LI.TQHT LI.RX86LSIELI.TQLT 126h LI.TQTIELI.TQCTLS 127h Ethernet Interface Register Bit Descriptions Ethernet Interface RegistersSU.MACRADL SU.MACRADH SU.MACRD2 SU.MACRD1SU.MACRD3 SU.MACWD0 SU.MACWD2 SU.MACWD1SU.MACWD3 SU.MACAWL SU.MACRWC SU.MACAWH SU.GCR SU.LPBK Transmit Frame Resend Control SU.TFRC151h Ncfq Tprhbc Tprcb SU.TFSH SU.TFSL SU.RFSB2 SU.RFSB0SU.RFSB1 MCF SU.RFSB3157h SU.RMFSRH SU.RMFSRLSU.RQLT SU.RQHT SU.QCRLS SU.QRIE Receive Frame Rejection Control SU.RFRC15Eh Ucfr Cfrr Lerr Crcerr DBR Miier BFR SU.MACCR MAC Registers Bit Random Number Generator Bits Used SU.MACMIIA SU.MACMIID SU.MACFCR SU.MMCCTRL MAC Reserved Control Register Reserved010Ch indirect 010Dh 0111h 0110h indirect0112h 0113h MAC All Frames Received Counter SU.RxFrmCtr0200h indirect 0201h MAC Frames Received OK Counter SU.RxFrmOkCtr0204h indirect 0205h MAC All Frames Transmitted Counter SU.TxFrmCtr0300h indirect 0301h MAC All Bytes Transmitted Counter SU.TxBytesCtr0308h indirect 0309h MAC Bytes Transmitted OK Counter SU.TxBytesOkCtr030Ch indirect 030Dh MAC Transmit Frame Under Run Counter SU.TxFrmUndr0334h indirect 0335h MAC All Frames Aborted Counter SU.TxBdFrmCtr0338h indirect 0339h Effect On Output Pins Master Mode Register11.7 T1/E1/J1 Transceiver Registers TR.MSTRREG Bit 6 Rsync Mode Select 2 RSMS2 Configuration RegisterTR.IOCR1 Bit 1 Tsync I/O Select Tsio 0 = Tsync is an input TR.IOCR2 OOF2 OOF1 TR.T1RCR1 Bit 5 Receive B8ZS Enable RB8ZS Bit 6 Receive Frame Mode Select RFM 0 = D4 framing modeBit 1 Receive Japanese CRC6 Enable RJC TR.T1RCR2 TR.T1TCR1 TB8ZS TSLC96 Tzse FBCT2 FBCT1 TD4YM TB7ZS Bit 7 Transmit B8ZS Enable TB8ZSTR.T1TCR2 TR.SSIE1 T1 Mode Bit 2 Transmit Frame Mode Select TFM 0 = D4 framing modeTR.T1CCR1 T1 Common Control Register TR.SSIE2 E1 Mode TR.SSIE1 E1 ModeSoftware Signaling Insertion Enable TR.SSIE4 TR.SSIE3 E1 ModeLcaw TR.T1RDMR3 TR.T1RDMR1TR.T1RDMR2 TR.INFO1 TR.IDR 11h TR.INFO2Bits 0 3 Receive Level Bits RL0 to RL3. Real-time bits RL3 RL2 RL1 RL0 TR.IIR2 TR.INFO3TR.IIR1 TR.SR1 Ilut Timer Rscos Jalt Lrcl Tcle Tocd LolitcStatus Register 16h Interrupt Mask Register TR.IMR117h Bit 7 Input Level Under Threshold Ilut 0 = interrupt masked Ryelc RUA1C Frclc Rlosc TR.SR218h Bit 0 Receive Loss-of-Sync Condition Rlos TR.IMR219h Lspare LDN LUP Lotc Lorc V52LNK Rdma RRA TR.SR31Ah TR.IMR3 1Ch TR.SR4RAIS-CI Rsao Rsaz TMF TAF RMF Rcmf RAF Bit 2 Receive Multiframe Event RMF 1Dh TR.IMR4Bit 7 Receive AIS-CI Event RAIS-CI Bit 3 Transmit Align Frame Event TAF 0 = interrupt masked Tesf Tesem Tslip Resf Resem Rslip TR.SR51Eh 1Fh TR.IMR5 Hdlc #1 Status Register TR.SR6, TR.SR7Hdlc #2 Status Register 20h, 22h TR.IMR6, TR.IMR7 TR.INFO4 TR.INFO5, TR.INFO6PS2 PS1 PS0 TR.IMR8 TR.SR8 Bbed Bbco BEC0 BRA1 BRA0 Brlos Bsync TR.SR926h TR.IMR9 Per-Channel Pointer Register TR.PCPR28h Rsaoics Rsrcs Rfcs Brcs Thscs Peics Tfcs Btcs TR.PCDR2 TR.PCDR1TR.PCDR3 TR.PCDR4 TR.H1RC, TR.H2RC TR.INFO7Hdlc #1 Receive Control Hdlc #2 Receive Control 31h, 32h TR.E1RCR2 TR.E1RCR1 TR.E1TCR1 RBF1 RBF0 TR.E1TCR2TR.BOCC TR.RSCSE1, TR.RSCSE2, TR.RSCSE3, TR.RSCSE4 TR.RSINFO1, TR.RSINFO2, TR.RSINFO3, TR.RSINFO4MSB LSB Grsre RFE RFF Rccs Tccs Frsao Signaling Control RegisterTR.SIGCR Bit 5 Error-Counter Update Select Ecus Error-Counter Configuration RegisterBit 4 Error-Accumulation Mode Select Eams Bit 2 Pcvcr Fs-Bit Error-Report Enable Fsbe TR.LCVCR2 TR.LCVCR1TR.PCVCR1 TR.PCVCR2 TR.FOSCR2 TR.FOSCR1TR.EBCR1 TR.EBCR2 Loopback Control Register TR.LBCR4Ah Liuc LLB RLB PLB FLB TR.PCLR2 TR.PCLR1TR.PCLR3 TR.PCLR4 Elastic Store Control Register TR.ESCR4Fh Tesalgn Tesr Tesmdm Tese Resalgn Resr Resmdm Rese 50h to 5Fh Transmit Signaling Registers E1 Mode, CAS FormatTR.TS1 to TR.TS16 Transmit Signaling Registers E1 Mode, CCS Format 50h to 5Bh Transmit Signaling Registers T1 Mode, ESF FormatTR.TS1 to TR.TS12 CH2-A CH2-B Transmit Signaling Registers T1 Mode, D4 FormatCH1-A CH1-B CH4-A CH4-B Receive Signaling Registers T1 Mode, D4 Format Receive Signaling Registers T1 Mode, ESF FormatTR.RS1 to TR.RS12 60h to 6Bh Receive Signaling Registers E1 Mode, CCS Format Receive Signaling Registers E1 Mode, CAS FormatTR.RS1 to TR.RS16 60h to 6Fh TCSS1 TCSS0 TR.CCR1 TR.CCR3 TR.CCR2BPCS1 BPCS0 TR.TDS0SEL TR.CCR4RLT3 RLT2 RLT1 RLT0 TR.RDS0M TR.TDS0MTR.RDS0SEL TR.LIC1 Network Mode GC5 GC4 GC3 GC2 GC1 GC0 Bit 6 Automatic Gain Control Enable AgceTR.TLBC T1, Impedance Match Off 79h TR.LIC2ETS Lirst Ibpv TUA1 Jamux Scld Clds Bit 7 E1/T1 Select ETS MM1 MM0 TR.LIC3 MPS1 MPS0 Jamux TR.LIC4Mclk MPS1 MPS0 Jamux TT1 TT0 Gric Gtic Function TR.IAARTR.PCICR TR.TCICE1 TR.TCICE3 TR.TCICE2TR.TCICE4 TR.RCICE1 TR.RCICE3 TR.RCICE2TR.RCICE4 TR.RCBR1 TR.RCBR4 TR.RCBR2TR.RCBR3 TR.TCBR2 TR.TCBR1TR.TCBR3 TR.TCBR4 Hdlc #1 Transmit Control TR.H1TC, TR.H2TCHdlc #2 Transmit Control 90h, A0h RFHWM2 RFHWM1 RFHWM0 TR.H1FC, TR.H2FCTFLWM2 TFLWM1 TFLWM0 A2h, A3h, A4h, A5h Register Name TR.H1RCS1, TR.H1RCS2, TR.H1RCS3, TR.H1RCS4Bit 3 Receive Hdlc Channel Select Bit Bit 2 Receive Hdlc Channel Select Bit Hdlc # 1 Receive Time Slot Bits/Sa Bits Select TR.H1RTSBS, TR.H2RTSBSHdlc # 2 Receive Time Slot Bits/Sa Bits Select 96h, A6h RCB8SE RCB7SE RCB6SE RCB5SE RCB4SE RCB3SE RCB2SE RCB1SE A7h, A8h, A9h, AAh Register Name TR.H1TCS1, TR.H1TCS2, TR.H1TCS3, TR.H1TCS4Bit 3 Transmit Hdlc Channel Select Bit Bit 2 Transmit Hdlc Channel Select Bit TR.H1RPBA, TR.H2RPBA TR.H1TTSBS, TR.H2TTSBS TR.H1RF, TR.H2RF TR.H1TF, TR.H2TF TR.IBCC TR.H1TFBA, TR.H2TFBATC1 TC0 RUP2 RUP1 RUP0 TR.TCD2 TR.TCD1Transmit Code Definition Register B8h BAh TR.RUPCD2Receive Up-Code Definition Register Receive Down-Code Definition Register TR.RDNCD1BBh TR.RDNCD2 In-Band Receive Spare Control Register TR.RSCCBDh RSC2 RSC1 RSC0 TR.RSCD2 TR.RSCD1 Receive FDL Register TR.RFDL TR.BOCC.4 =C0h RBOC5 RBOC4 RBOC3 RBOC2 RBOC1 RBOC0 TR.RFDLM1, TR.RFDLM2 TR.TFDL Receive Align Frame Register TR.RAFC6h TR.RNAF Received Si Bits of the Align Frame TR.RSiAFC8h TR.RSiNAF TR.RRA Received Sa5 Bits TR.RSa5CCh TR.RSa6 Received Sa7 Bits TR.RSa7CEh TR.RSa8 TR.TNAF TR.TAF Transmit Si Bits of the Align Frame TR.TSiAFD2h TR.TSiNAF TR.TRA Transmitted Sa5 Bits TR.TSa5D6h TR.TSa6 Transmit Sa7 Bits TR.TSa7D8h TR.TSa8 TR.BAWC TR.TSACR TR.BRP2 TR.BRP1TR.BRP3 TR.BRP4 PS1 PS0 TR.BC1 RPL3 RPL2 RPL1 RPL0 TR.BC2EIB2 EIB1 EIB0 TR.BBC2 TR.BBC1TR.BBC3 TR.BBC4 EC7 EC6 EC5 EC4 EC3 EC2 EC1 EC0 TR.BEC1TR.BEC2 EC9 EC8 TR.BIC ER3 ER2 ER1 ER0 TR.ERC TR.NOE1 Number-of-ErrorsECh TR.NOE2 TR.NOEL2 TR.NOEL1 Tx Serial Interface Functional Timing Functional Serial I/O Timing MII and Rmii Interfaces Transmit Byte Sync Functional Timing MII Transmit Half Duplex with a Collision Functional Timing FRAME# RSYNC1 Rfsync RSYNC2 Rsync FRAME# Rfsync RSYNC1 Rsync 2 RSYNC3 Rchclk Rchblk Rsync RfsyncRchclk RCHBLK1 Rchclk RCHBLK4 Rsysclk Rser O Tchclk Tchblk FRAME# TSYNC1 Tssync Tsync TSYNC3 Tchclk Tchblk 2,3 FRAME# Rfsync Rsync 12.4 E1 Mode RSYNC2 Rmsync RSYNC3 Rchclk Rchblk Rsysclk RseroRmsync Rsync Rchclk RCHBLK3 TSYNC2 Rsync Tsync Rchclk Tchclk Rchblk TchblkFRAME# TSYNC1 Tssync Tssync Tchclk Tchblk 26. Transmit-Side Boundary Timing Elastic Store Disabled 312 Recommended DC Operating Conditions DC Electrical CharacteristicsParameter Symbol Conditions MIN TYP MAX Units Theta-JA vs. Airflow Thermal Characteristics -3. Thermal CharacteristicsParameter MIN TYP MAX AIR Flow THETA-JA MII Interface Transmit MII Interface Parameter Symbol10Mbps 100Mbps MIN TYP MAX Receive MII Interface Timing Receive MII Interface Transmit Rmii Interface Timing Rmii Interface Transmit Rmii Interface Receive Rmii Interface Timing Receive Rmii Interface MDC Mdio Parameter Symbol MIN TYP MAX UnitsMdio Interface Tclke Tsero Tden Tbsync Transmit WAN Interface 10. Transmit WAN Interface Rclki Rseri Rden Rbsync Receive WAN Interface 11. Receive WAN Interface 100 MHz Sdram Timing 12. Sdram Interface Timing RAS, Scas SdataSWE, Sdcs SDA, SBA Parameter Symbol MIN TYP MAX Units Intel Bus Read Timing Modec = 11. Motorola Bus Read Timing Modec = RMSYNC, Rsync RCHBLK, Rfsync Rfsync / Rmsync Rsero / Rdata / Rsig Rchblk Rmsync Rsync Rsero / RsigSee Note 15. Receive Line Interface Timing Delay Rclko to Bpclk 16. Receive Timing Delay Rclko to Bpclk TSERI, TSIG, TDATA, TPOSI, Tnegi Parameter Symbol Conditions MIN TYP E1 MAX Units 17. Transmit-Side Timing 18. Transmit-Side Timing, Elastic Store Enabled Jtag Interface Timing 17. Jtag Interface Timing 20. Jtag Interface Timing Diagram Jtag Information Jtag TAP Controller State Machine Description Update-IR Update-DRSelect-IR-Scan Capture-IR Instruction Register TAP Controller State Diagram Instruction Selected Register Instruction Codes Instruction Codes for Ieee 1149.1 Architecture Test Registers Jtag ID Codes ID Code StructureBoundary Scan Register Bypass Register Bypass Idcode State Jtag Functional Timing 15.1 256-Ball BGA 27mm x 27mm 56-G6004-001 Package Information Revision Description Document Revision History