DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver

Table 11-8. T1/E1/J1 Transceiver Register Bit Map (Active when CST = 0)

ADD

NAME

BIT 7

BIT 6

BIT 5

BIT 4

R

 

 

 

 

 

000

 

h

TR.MSTRREG

 

 

 

 

001

 

RSMS

RSMS2

RSMS1

RSIO

h

TR.IOCR1

 

 

 

 

002

 

RDCLKIN

TDCLKIN

RSYNCINV

TSYNCINV

h

TR.IOCR2

V

V

 

 

003

 

ARC

OOF1

OOF2

h

TR.T1RCR1

 

 

 

 

004

 

RFM

RB8ZS

RSLC96

h

TR.T1RCR2

 

 

 

 

005

 

TJC

TFPT

TCPT

TSSE

h

TR.T1TCR1

 

 

 

 

006

 

TB8ZS

TSLC96

TZSE

FBCT2

h

TR.T1TCR2

 

 

 

 

007

 

TRAI-CI

h

TR.T1CCR1

 

 

 

 

008

TR.SSIE1-T1

CH8

CH7

CH6

CH5

h

TR.SSIE1-E1

CH7

CH6

CH5

CH4

009

TR.SSIE2-T1

CH16

CH15

CH14

CH13

h

TR.SSIE2-E1

CH15

CH14

CH13

CH12

00A

TR.SSIE3-T1

CH24

CH23

CH22

CH21

h

TR.SSIE3-E1

CH22

CH21

CH20

CH19

00B

 

CH30

CH29

CH28

CH27

h

TR.SSIE4

 

 

 

 

00C

 

CH8

CH7

CH6

CH5

h

TR.T1RDMR1

 

 

 

 

00D

 

CH16

CH15

CH14

CH13

h

TR.T1RDMR2

 

 

 

 

00E

 

CH24

CH23

CH22

CH21

h

TR.T1RDMR3

 

 

 

 

00F

 

ID7

ID6

ID5

ID4

h

TR.IDR

 

 

 

 

010

 

RPDV

TPDV

COFA

8ZD

h

TR.INFO1

 

 

 

 

011

 

BSYNC

BD

TCLE

TOCD

h

TR.INFO2

 

 

 

 

012

 

h

TR.INFO3

 

 

 

 

013

 

h

Reserved

 

 

 

 

014

 

SR8

SR7

SR6

SR5

h

TR.IIR1

 

 

 

 

015

 

h

TR.IIR2

 

 

 

 

016

 

ILUT

TIMER

RSCOS

JALT

h

TR.SR1

 

 

 

 

017

 

ILUT

TIMER

RSCOS

JALT

h

TR.IMR1

 

 

 

 

018

 

RYELC

RUA1C

FRCLC

RLOSC

h

TR.SR2

 

 

 

 

019

TR.IMR2

RYELC

RUA1C

FRCLC

RLOSC

BIT 3

TEST1

TSDW

TSSYNCINV

SYNCC

RZSE

GB7S

FBCT1

TAIS-CI

CH4

CH3

CH12

CH11

CH20

CH18

CH26

CH4

CH12

CH20

ID3

16ZD

RL3

SR4

LRCL

LRCL

RYEL

RYEL

BIT 2

BIT 1

BIT 0

 

 

 

TEST0

T1/E1

SFTRST

 

 

 

TSM

TSIO

ODF

 

 

 

H100EN

TSCLKM

RSCLKM

 

 

 

SYNCT

SYNCE

RESYNC

 

 

 

RJC

RD4YM

 

 

 

TFDLS

TBL

TYEL

 

 

 

TD4YM

Reserved

TB7ZS

 

 

 

TFM

PDE

TLOOP

 

 

 

CH3

CH2

CH1

CH2

CH1

UCAW

CH11

CH10

CH9

CH10

CH9

CH8

CH19

CH18

CH17

CH17

CH16

LCAW

CH25

CH24

CH23

 

 

 

CH3

CH2

CH1

 

 

 

CH11

CH10

CH9

 

 

 

CH19

CH18

CH17

 

 

 

ID2

ID1

ID0

 

 

 

SEFE

B8ZS

FBE

 

 

 

RL2

RL1

RL0

 

 

 

CRCRC

FASRC

CASRC

 

 

 

 

 

 

SR3

SR2

SR1

 

 

 

SR9

 

 

 

TCLE

TOCD

LOLITC

 

 

 

TCLE

TOCD

LOLITC

 

 

 

RUA1

FRCL

RLOS

 

 

 

RUA1

FRCL

RLOS

125 of 344

Page 125
Image 125
Maxim DS33R11 specifications T1/E1/J1 Transceiver Register Bit Map Active when CST =, 019