DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver

 

 

 

 

 

 

 

NAME

PIN

TYPE

FUNCTION

 

TXD[0]

F19

 

Transmit Data 0 through 3(MII): TXD [3:0] is presented

 

 

 

 

 

synchronously with the rising edge of TX_CLK. TXD [0] is the least

 

 

TXD[1]

F18

 

 

O

significant bit of the data. When TX_EN is low the data on TXD

 

 

 

 

should be ignored.

 

 

TXD[2]

E20

 

 

 

 

 

 

 

 

Transmit Data 0 through 1(RMII): Two bits of data TXD [1:0]

 

 

TXD[3]

E19

 

 

 

 

presented synchronously with the rising edge of REF_CLK.

 

 

 

 

 

 

 

 

 

 

Transmit Enable (MII): This pin is asserted high when data TXD

 

 

 

 

 

[3:0] is being provided by the DS33R11. The signal is deasserted

 

 

 

 

 

prior to the first nibble of the next frame. This signal is synchronous

 

 

TX_EN

F20

O

with the rising edge TX_CLK. It is asserted with the first bit of the

 

 

preamble.

 

 

 

 

 

 

 

 

 

 

Transmit Enable (RMII): When this signal is asserted, the data on

 

 

 

 

 

TXD [1:0] is valid. This signal is synchronous to the REF_CLK.

 

 

 

 

 

Reference Clock (RMII and MII): When in RMII mode, all signals

 

 

 

 

 

from the PHY are synchronous to this clock input for both transmit

 

 

 

 

 

and receive. This required clock can be up to 50MHz and should

 

 

 

 

 

have ±100ppm accuracy.

 

 

REF_CLK

A19

I

When in MII mode in DCE operation, the DS33R11 uses this input

 

 

to generate the RX_CLK and TX_CLK outputs as required for the

 

 

 

 

 

 

 

 

 

 

Ethernet PHY interface. When the MII interface is used with DTE

 

 

 

 

 

operation, this clock is not required and should be tied low.

 

 

 

 

 

In DCE and RMII modes, this input must have a stable clock input

 

 

 

 

 

before setting the RST pin high for normal operation.

 

 

 

 

 

Reference Clock Output (RMII and MII): A derived clock output

 

 

REF_CLKO

A20

O

up to 50MHz, generated by internal division of the SYSCLKI signal.

 

 

Frequency accuracy of the REF_CLKO signal will be proportional

 

 

 

 

 

to the accuracy of the user-supplied SYSCLKI signal. See Section

 

 

 

 

 

9.1.1 for more information.

 

 

 

 

 

DCE or DTE Selection: The user must set this pin high for DCE

 

 

 

 

 

Mode selection or low for DTE Mode. In DCE Mode, the DS33R11

 

 

DCEDTES

G20

I

MAC port can be directly connected to another MAC. In DCE

 

 

Mode, the Transmit clock (TX_CLK) and Receive clock (RX_CLK)

 

 

 

 

 

are output by the DS33R11. Note that there is no software bit

 

 

 

 

 

selection of DCEDTES. Note that DCE Mode is only relevant when

 

 

 

 

 

the MAC interface is in MII mode.

 

 

RMIIMIIS

G19

I

RMII or MII Selection: Set high to configure the MAC for RMII

 

 

interfacing. Set low for MII interfacing.

 

 

 

 

 

 

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Image 28
Maxim DS33R11 Transmit Data 0 through 3MII TXD 30 is presented, Transmit Data 0 through 1RMII Two bits of data TXD