Maxim DS33R11 specifications Name PIN Type Function MII/RMII PHY Port

			DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
NAME	PIN	TYPE	FUNCTION
			MII/RMII PHY PORT
			Collision Detect (MII): Asserted by the MAC PHY to indicate that a
COL_DET	N18	I	collision is occurring. In DCE Mode this signal should be connected
			to ground. This signal is only valid in half duplex mode, and is
			ignored in full duplex mode.
			Receive Carrier Sense (MII): Should be asserted (high) when data
			from the PHY (RXD[3:0) is valid. For each clock pulse 4 bits arrive
RX_CRS/			from the PHY. Bit 0 is the least significant bit. In DCE mode,
	M19	I	connect to VDD.
CRS_DV
			Carrier Sense/Receive Data Valid (RMII): This signal is asserted
			(high) when data is valid from the PHY. For each clock pulse 2 bits
			arrive from the PHY. In DCE mode, this signal must be grounded.
			Receive Clock (MII): Timing reference for RX_DV, RX_ERR and
			RXD[3:0], which are clocked on the rising edge. RX_CLK frequency
RX_CLK	M20	IO	is 25MHz for 100Mbit/s operation and 2.5MHz for 10Mbit/s
			operation. In DTE mode, this is a clock input provided by the PHY.
			In DCE mode, this is an output derived from REF_CLK providing
			2.5MHz (10Mbit/s operation) or 25MHz (100Mbit/s operation).
RXD[0]	L18		Receive Data 0 through 3 (MII): Four bits of received data,
			sampled synchronously with the rising edge of RX_CLK. For every
			clock cycle, the PHY transfers 4 bits to the DS33R11. RXD[0] is the
RXD[1]	L19		least significant bit of the data. Data is not considered valid when
			RX_DV is low.
		O
RXD[2]	L20		Receive Data 0 through 1 (RMII): Two bits of received data,
			sampled synchronously with REF_CLK with 100Mbit/s mode.
RXD[3]	M18		Accepted when CRS_DV is asserted. When configured for
			10Mbit/s mode, the data is sampled once every 10 clock periods.
RX_DV	K19	I	Receive Data Valid (MII): This active high signal indicates valid
			data from the PHY. The data RXD is ignored if RX_DV is not
			asserted high.
			Receive Error (MII): Asserted by the MAC PHY for one or more
			RX_CLK periods indicating that an error has occurred. Active High
RX_ERR	K18	I	indicates Receive code group is invalid. If CRS_DV is low,
			RX_ERR has no effect. This is synchronous with RX_CLK. In DCE
			mode, this signal must be grounded.
			Receive Error (RMII): Signal is synchronous to REF_CLK.
			Transmit Clock (MII): Timing reference for TX_EN and TXD[3:0].
			The TX_CLK frequency is 25MHz for 100Mbit/s operation and
TX_CLK	H19	IO	2.5MHz for 10Mbit/s operation.
			In DTE mode, this is a clock input provided by the PHY. In DCE
			mode, this is an output derived from REF_CLK providing 2.5MHz
			(10Mbit/s operation) or 25MHz (100Mbit/s operation).

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