Maxim DS33R11 specifications Tr.Bic

	DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
Register Name:	TR.BIC
Register Description:	BERT Interface Control Register
Register Address:	EAh

Bit #

Name

Default

7	6	5	4	3	2	1	0
—	RFUS	—	TBAT	TFUS	—	BERTDIR	BERTEN
0	0	0	0	0	0	0	0

Bit 6: Receive Framed/Unframed Select (RFUS)

0 = BERT is not sent data from the F-bit position (framed) 1 = BERT is sent data from the F-bit position (unframed)

Bit 4: Transmit Byte-Align Toggle (TBAT). A 0-to-1 transition forces the BERT to byte align its pattern with the transmit formatter. This bit must be transitioned in order to byte align the Daly pattern.

Bit 3: Transmit Framed/Unframed Select (TFUS)

0 = BERT does not source data into the F-bit position (framed) 1 = BERT does source data into the F-bit position (unframed)

Bit 1: BERT Direction (BERTDIR)

0 = network

BERT transmits toward the network (TTIP and TRING) and receives from the network (RTIP and RRING). The BERT pattern can be looped back to the receiver internally by using the framer loopback function.

1 = system

BERT transmits toward the system backplane (RSERO) and receives from the system backplane (TSERI).

Bit 0: BERT Enable (BERTEN)

0 = BERT disabled

1 = BERT enabled

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