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GENERAL DESCRIPTION
The DS33R11 extends a 10/100 Ethernet LAN
segment by encapsulating MAC frames in HDLC or
X.86 (LAPS) for transmission over a T1/E1/J1 data
stream.
The device performs store-and-forward of packets
with full wire-speed transport capability. The built-in
Committed Information Rate (CIR) Controller
provides fractional bandwidth allocation up to the line
rate in increments of 512kbps. The DS33R11 can
operate with an inexpensive external processor.
APPLICATIONS
Transparent LAN Service
LAN Extension
Ethernet Delivery Over T1/E1/J1
FUNCTIONAL DIAGRAM
FEATURES
10/100 IEEE 802.3 Ethernet MAC (MII and
RMII) Half/Full Duplex with Automatic Flow
Control
Integrated T1/E1/J1 Framer and LIU
HDLC/LAPS Encapsulation with
Programmable FCS and Interframe Fill
Committed Information Rate Controller
Provides Fractional Allocations in 512kbps
Increments
Programmable BERT for Serial (TDM)
Interface
External 16MB, 100MHz SDRAM Buffering
Parallel Microprocessor Interface
1.8V, 3.3V Supplies
Reference Design Routes on Two Signal
Layers
10/100
MAC
SDRAM
MII/RMII
μC
DS33R11
10/100
ETHERNET
PHY
SERIAL STREAM T1/E1/J1
TRANSCEIVER
BERT
HDLC/X.86
MAPPER
T1/E1
LINE
IEEE 1149.1 JTAG Support
Features continued on page 11.
ORDERING INFORMATION
PART TEMP RANGE PIN-PACKAGE
DS33R11 -40°C to +85°C 256 BGA
1 of 344 REV: 030807
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.