Maxim DS33R11 specifications Tr.Pcpr, Per-Channel Pointer Register, 28h

	DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
Register Name:	TR.PCPR
Register Description:	Per-Channel Pointer Register
Register Address:	28h

Bit #

Name

Default

7	6	5	4	3	2	1	0
RSAOICS	RSRCS	RFCS	BRCS	THSCS	PEICS	TFCS	BTCS
0	0	0	0	0	0	0	0

Bit 7: Receive Signaling All-Ones Insertion Channel Select (RSAOICS)

Bit 6: Receive Signaling Reinsertion Channel Select (RSRCS)

Bit 5: Receive Fractional Channel Select (RFCS)

Bit 4: Bert Receive Channel Select (BRCS)

Bit 3: Transmit Hardware Signaling Channel Select (THSCS)

Bit 2: Payload Error Insert Channel Select (PEICS)

Bit 1: Transmit Fractional Channel Select (TFCS)

Bit 0: Bert Transmit Channel Select (BTCS)

See Section 10.2 for a general overview of per-channel operation. See Section 10.10 for more information on per- channel idle code generation. See Section 10.6 for more information on per-channel loopback operation.

231 of 344