DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver

Figure 12-22. Receive-Side Boundary Timing, RSYSCLK = 1.544MHz (E-Store Enabled)

RSYSCLK

RSERO1

CHANNEL 23/31

CHANNEL 24/32

CHANNEL 1/2

LSB MSB

LSB

F MSB

RSYNC2

RMSYNC

RSYNC3

RCHCLK

RCHBLK 4

NOTE 1: DATA FROM THE E1 CHANNELS 1, 5, 9, 13, 17, 21, 25, AND 29 IS DROPPED (CHANNEL 2 FROM THE E1 LINK IS

MAPPED TO CHANNEL 1 OF THE T1 LINK, ETC.) AND THE F-BIT POSITION IS ADDED (FORCED TO ON 1).

NOTE 2: RSYNC IN THE OUTPUT MODE (TR.IOCR1.4 = 0).

NOTE 3: RSYNC IN THE INPUT MODE (TR.IOCR1.4 = 1).

NOTE 4: RCHBLK IS PROGRAMMED TO BLOCK CHANNEL 24.

Figure 12-23. Receive-Side Boundary Timing, RSYSCLK = 2.048MHz (E-Store Enabled)

RSYSCLK

 

CHANNEL 31

CHANNEL 32

CHANNEL 1

RSERO

LSB MSB

LSB MSB

RSYNC1

 

 

 

RMSYNC

 

 

 

RSYNC2

 

 

 

 

CHANNEL 31

CHANNEL 32

CHANNEL 1

RSIG

A B C D

A B C

D

 

 

 

Note 4

RCHCLK

RCHBLK3

NOTE 1: RSYNC IS IN THE OUTPUT MODE (TR.IOCR1.4 = 0).

NOTE 2: RSYNC IS IN THE INPUT MODE (TR.IOCR1.4 = 1).

NOTE 3: RCHBLK IS PROGRAMMED TO BLOCK CHANNEL 1.

NOTE 4: RSIG NORMALLY CONTAINS THE CAS MULTIFRAME ALIGNMENT NIBBLE (0000) IN CHANNEL 1.

309 of 344

Page 309
Image 309
Maxim DS33R11 specifications Rsysclk Rsero, RSYNC2 Rmsync RSYNC3 Rchclk Rchblk, Rmsync Rsync, Rchclk RCHBLK3