(2) ADU CPU (IC1)

1. Outline

The CPU controls the loads of the ADU unit and performs data trans- mission through the copier main PWB and the serial data line to make synchronization with data transmission to control the ADU unit.

2. Feature

The H8/3297 series is a single chip microcomputer which integrates the H8/300CPU and the peripheral devices.

3. Internal block diagram

FIg. 1.1 shows the internal block diagram of the LSI.

Fig. 1.1 Internal block diagram

CPU

H8/300

Data bus (Lower)

P40/IRQ2/ADTRG

P10/A0

P11/A1

P12/A2

P13/A3

P14/A4

ROM

RAM

P41/IRQ1

P42/IRQ0

P43/RD

P44/WR

P45/AS

P15/A5

P16/A6

P17/A7

P20/A8

P21/A9

P22/A10

P23/A11

P24/A12

P25/A13

P26/A14

P27/A15

Watch-dog

timer

16-bit free

running timer

8-bit timer

x 2ch

Serial

communication

interface

10-bit A/D convertor x 8ch

P46/ φ

P47/WAIT

P30/D0

P31/D1

P32/D2

P33/D3

P34/D4

P35/D5

P36/D6

P37/D7

Port 6

Port 7

Port 5

12 – 18

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Sharp SF-1020, SF-1120 service manual ADU CPU IC1, Rom Ram