Siemens SM2 monitoring system manual Glossary Processor states, Response time, Risc mode

Glossary

processor states

Program interrupts are caused by

–input/output requests

–calls to the Control System

–timers

–errors

–paging requests

The system distinguishes between the following processor states when handling programs and interrupts:

TU TPR SIH MEH

Processor	Processor	Recognition	Recognition
state for	state for program	state for program	state for
user programs	interrupts	interrupts	machine errors
Interruptible	Interruptible;	Interruptible	Non-
	in part	by MER only	interruptible
	non-interruptible
Nonprivileged	Privileged processor states

If the CPU is in none of the above states, it is in the IDLE state.

response time

Time required by the system for processing a request. For the user, this is the time between an input operation and the corresponding system response (see “RESPON- SETIME Monitored data on the BCAM pool” on page 45 and “BCAM-CONNECTION Monitored data on connection sets” on page 35).

RISC mode

Runtime environment of a RISC processor.

454 U3585-J-Z125-8-76