SNC 5100

POST Error Codes

The Power-On-Self-Test (POST) is responsible for testing the integrity of the processor’s SDRAM. After testing SDRAM POST will attempt to transfer control to either the default bootrom image or an alternate image.

POST can also download binary images over the service port and write them to flash memory. This enables POST to perform a minimal amount of emergency recovery from FLASH errors.

POST Boot Behavior

ROM Init

Figure 10 ROM Init

After applying power the ERR LED will illuminate.

At this time postInit code initializes the processor’s internal registers and subsystems, including the SDRAM controller.

The processor’s internal RAM is used as a tiny-stack for this stage of POST.

Control is then passed to the IpostMain routine for the SDRAM memory.

POST Boot Behavior 197

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ADIC SNC 5100, Scalar 1000 manual Post Boot Behavior, ROM Init