HP unix manual CPU n is starting its interval timer

Troubleshooting

Selftest Failures

Table 3-2. Chassis Codes for the B2000 Workstation

Ostat	Code	FRU	Message	Description
TST	1n27	SYS BD	CPUn itimer test	CPU n is starting its interval timer
				self-test.
TST	1n28	SYS BD	CPUn multi-media	CPU n is starting its multi-media
				instructions self-test.
TST	1n29	SYS BD	CPUn shadow reg	CPU n is starting its shadow register
				self-test.
TST	1n2A	SYS BD	CPUn diagnse reg	CPU n is starting its diagnose register
				self-test.
TST	1n2B	SYS BD	CPUn rdr test	CPU n is starting its remote diagnose
				register self-test.
TST	1n2C	SYS BD	CPUn bypass test	CPU n is starting its integer bypass
				operation self-test.
TST	1n30	SYS BD	CPUn start est	CPU n is starting its early (pre-memory)
				self-tests.
WRN	1n31	SYS BD	CPUn skip est	CPU n is bypassing its early self-tests to
				save time.
FLT	1n32	SYS BD	CPUn bad tst mod	CPU n detected an unsupported system
				mode.
INI	1n3C	SYS BD	CPUn initialize	CPU n is initializing after self-tests.
TST	1n3E	SYS BD	CPUn exit est	CPU n finished its early self-tests.
TST	1nA0	SYS BD	CPUn fpu tests	CPU n is starting its floating-point unit
				self-tests.
TST	1nA1	SYS BD	CPUn fpu reg tst	CPU n is starting its floating-point
				register self-test.
TST	1nA2	SYS BD	CPUn fpu inst	CPU n is starting its floating-point
				instruction self-test.
TST	1nA3	SYS BD	CPUn fpu traps	CPU n is starting its floating-point trap
				self-test.
TST	1nA4	SYS BD	CPUn fpu misc	CPU n is starting its floating-point
				miscellaneous operations self-test.
TST	1nA5	SYS BD	CPUn fpu bypass	CPU n is starting its floating-point
				bypassing self-test.
TST	1nB1	SYS BD	CPUn TLB RAM tst	CPU n is starting its TLB register
				self-test.
TST	1nB2	SYS BD	CPUn TLB trans	CPU n is starting its TLB translation
				self-test.

56 Chapter 3