Agilent Technologies 1690, 1680 manual 1682A,AD or 1692A,AD only, Pod 1 clock/data channel Clk

Models: 1690 1680

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*1682A,AD or 1692A,AD only.

Chapter 3: Testing Performance

To test the single-clock, single-edge, state acquisition

Connect the 1682/83/92/93A,AD Logic Analyzer to the Pulse Generator

Testing

Connect to 8133A

Connect to 8133A

Connect to 8133A

Combination

Channel 2 Output

Channel 2 Output

Channel 1 Output

1

Pod 1, channel 3

 

Pod 2, channel 3

 

Pod 3, channel 3

 

Pod 4, channel 3

*1682A,AD or 1692A,AD only.

Pod 1, channel 11 Pod 2, channel 11 Pod 3, channel 11* Pod 4, channel 11*

Pod 1 clock/data channel (Clk 1)

3Activate the data channels that are connected according to one of the previous tables:

a Click on the Pod 1 clock/data channel (Clk 1) Bus/Signal Setup icon. The Analyzer Setup dialog opens. b In the Buses/Signals tab, click Delete All at the bottom of the dialog.

c Using the mouse, activate the data channels being tested. Assign channels to bus/signal name My Bus 1.

d Click OK to close the Analyzer Setup dialog.

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Agilent Technologies 1690, 1680 manual 1682A,AD or 1692A,AD only, Pod 1 clock/data channel Clk