Chapter 3: Testing Performance

To test the single-clock, multiple-edge, state acquisition

Test the next channels (1680/81A,AD and 1690/91A,AD)

Connect the next combination of data channels and clock channels, then repeat the previous test.

Start with “Connect and configure the logic analyzer” on page 58, connect the next combination, then continue through the complete test.

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Agilent Technologies manual Test the next channels 1680/81A,AD and 1690/91A,AD