Chapter 8: Theory of Operation
Trigger Arm Test. The Trigger Arm Test verifies that the local arm signal can be received by the master acquisition IC on the acquisition board. The test also verifies the global arm signal can be driven by each acquisition IC on a master board and received by all acquisition ICs on the card. The arm lines are asserted and read at the acquisition ICs to ensure each acquisition IC recognizes the signal.
Passing the Trigger Arm Test implies any acquisition IC can arm the card and that all acquisition ICs can recognize the arm signal.
Clock Paths Test. The Clock Paths Test verifies that the system Master, Slave, and Psync clocks are functional between the acquisition ICs. The module is configured to take a simple measurement. Test data is then created at the comparators and an acquisition taken. The resulting data is then downloaded and compared with known values.
Passing the Clock Paths Test implies that all acquisition IC clock lines can be driven by each acquisition IC and can be received by each acquisition IC in the module. Consequently each acquisition IC can reliably acquire data in response to the acquisition clock signal.
Memory Modes Test. The Memory Modes Test verifies the CPU interface can properly manage the acquisition memory unload in full channel,
Passing the Memory Modes Test implies that the data can be reliably read from acquisition memory in full channel,
Calibration Test. The Calibration Test ensures that each acquisition IC in the module can perform an operational accuracy
Passing the Calibration Test implies that the module can reliably perform an operation accuracy
Logic Analyzer Self-Tests
Register Test. The Register Test verifies that the registers of each acquisition IC is operating properly. Test patterns are written to each register on each acquisition IC, read, and compared with know values. The registers are reset, and